RT9241A RICHTEK [Richtek Technology Corporation], RT9241A Datasheet - Page 12

• Manufacturer Part Number: RT9241A
• Description: Two-Phase DC/DC Controller for CPU Core Power Supply
• Manufacturer: RICHTEK [Richtek Technology Corporation]

COMP
RT9241A/B
The sensing circuit gets
R
amplifier input bias current. I
before low side MOSFET turns off (See Figure 2).
Therefore,
period = T
Droop tuning
The S/H current signals from power channels are injected
to ADJ pin to create droop voltage.
The DAC output voltage decreases by V
VCORE load droop(see Figure 3).
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12
SP
I
I
T
V
X(S/H)
X(S/H)
OFF
ADJ
= R
Figure 2. Inductor Current and PWM Signal
= (
= R
PWM Signal & High Side MOSFET Gate Signal
=
= I
SN
I
⎡
⎢
⎢
⎢
⎣
S
EA
V - V
L(S/H)
ADJ
to cancel the voltage drop caused by GM
L(AVG)
V
IN
-
+
V
DAC
R
Low Side MOSFET Gate Signal
Figure 3. Droop Tune Circuit
IN
×
SP
FB
-V
×
2
3
O
Falling Slope = Vo/L
R
ADJ
Inductor Current
-
Σ
)
S
V - (
I
×
+
X
O
T
V
-
S
DAC
V - V
, for switching
I
X
IN
I
V
L(S/H)
2
V
=
IN
ADJ
L
X
I
L
R
is sampled and held just
O
×
S P
= I
ADJ
) T
R
R
×
ADJ
Σ
S
L(AVG)
I
L (S/H)
Ix
S
I
L
Σ
by local feedback.
⎤
⎥
⎥
⎥
⎦
×
-
ADJ
R
R
V
L
SP
S
O
to form the
I
×
L (AVG)
T
OFF
2
2/3 I
2/3 I
X1
X2
Protection and SS function
For OVP, the RT9241A/B detects the V
Eliminate the parasitic delay and noise influence on the
PCB path for fast and accurate detection. The trip point
of OVP is 120% of normal output level. The PWM outputs
are pulled low to turn on the low side MOSFET and turn
off the high side MOSFET of the synchronous rectifier at
OVP. The OVP latch can only be reset by V
restart power on reset sequence. The PGOOD detection
trip point of V
PGOOD open drain output pulls low when V
the range.
Soft start circuit generates a ramp voltage by charging
external capacitor with 10uA current after IC POR acts.
The PWM pulse width and V
rising ramp to reduce the in-rush current and protect the
power components.
OCP is triggered if one channel S/H current signal
I
impedance to turn off both high and low side MOSFET in
the power stage and initial the hiccup mode protection.
The SS pin voltage is pulled low with a 10μA current
after it is less than 90% V
SS pin voltage < 0.2V. Three times of OCP disable the
converter and only release the latch by POR acts (see
Figure 4).
X
> 75μA. Controller forces PWM output latched at high
4V
2V
0V
0A
V
COUNT = 1 COUNT = 2
I
CORE
L
CORE
T0T1
is ±8% out of the normal level. The
OVERLOAD
APPLIED
Figure 4
T2
DD
TIME
. The converter restarts after
DS9241AB-05 March 2007
CORE
COUNT = 3
T3T4
are clamped by the
CORE
SS
OCRE
by V
DD
exceeds
SEN
or V
pin.
DVD