RT9644 RICHTEK [Richtek Technology Corporation], RT9644 Datasheet - Page 11

• Manufacturer Part Number: RT9644
• Description: ACPI Regulator/Controller for Dual Channel DDR Memory Systems
• Manufacturer: RICHTEK [Richtek Technology Corporation]

V
TT_GMCH/CPU
Application Information
Overview
The RT9644/A provides complete control, drive, protection
and ACPI compliance for a regulator powering DDR memory
systems and the GMCH core and GMCH/CPU termination
rails. It is primarily designed for computer applications
powered from an ATX power supply.
A 250kHz Synchronous Buck Regulator with a precision
0.8V reference provides the proper Core voltage to the
system memory of the computer. An internal LDO regulator
with the ability to both sink and source current and an
externally available buffered reference that tracks the
VDDQ output by 50% provides the VTT termination
voltage.
In RT9644, a two-stage LDO controller provides the GMCH
core voltage. A third LDO controller is included for the
regulation of the GMCH/CPU termination voltage.
In RT9644A, a second 250kHz PWM Buck regulator,
which requires an external MOSFET driver, provides the
GMCH core voltage. This PWM regulator is 90 out of
phase with the PWM regulator used for the Memory core.
Two additional LDO controllers are included, one for the
regulation of the GMCH/CPU termination rail and the
second for the DAC.
ACPI State Transitions
sleep signals and through monitoring of the 12V ATX bus.
Figure 1 and Figure 2 shows how the RT9644 and RT9644A
individual regulators are controlled during all state
transitions.
DS9644/A-01 August 2007
DDR_VTT
ACPI compliance is realized through the S3# and S5#
VIDPGD
V
V
GMCHH
P12V
V
GMCH
S5#
S3#
DDQ
Figure 1. Timing diagram for RT9644
t0t1
t2t3t4t5t6
t7
t8t9
>3T
T
SS
SS
t10
t11
t12
t13
t14
Preliminary
t15
V
TT_GMCH/CPU
DDR_VTT
S5 to S0 Transition
At the onset of a mechanical start, time t0 in Figure 1,
the RT9644 receives its bias voltage from the 5V Standby
bus (5VSBY). Once the 5VSBY rail has exceeded the
POR threshold, the RT9644 will remain in an internal S5
state until both the S3# and S5# signal have transitioned
high and the 12V POR threshold has been exceeded by
the +12V rail from the ATX, which occurs at time t1.
Once all of these conditions are met, the PWM error
amplifier will first be reset by internally shorting the COMP
pin to the FB pin. This reset lasts for 3-4 soft-start cycles,
Then digital soft-start sequence will begin. Each regulator
is enabled and soft-started according to a preset
sequence.
At time t2 the V
RT9644 are digitally soft-started.
The digital sof t-start f or the PW M regulator is
accomplished by clamping the error amplifier reference
input to a level proportional to the internal digital soft-start
voltage. As the soft-start voltage slews up, the PWM
comparator generates PHASE pulses of increasing width
that charge the output capacitor(s).
This method provides a rapid and controlled rising output
voltage. The linear regulators, with the exception of the
internal DDR_VTT LDO, are soft-started in a similar manner.
The error amplifier reference is clamped to the internal
digital soft-start voltage. As the soft-start voltage ramps
up, the respective DRIVE pin voltages increase, thus
enhancing the N-MOSFETs and charging the output
VIDPGD
V
V
GMCH
P12V
V
DDQ
S5#
S3#
DAC
Figure 2. Timing diagram for RT9644A
t0t1
t2t3t4t5t6
DDQ
rail and the upper V
t7
t8t9
RT9644/A
>3T
SS
GMCH
T
www.richtek.com
SS
t10
t11
t12
LDO rail of
t13
t14
11
t15