HT1380A HOLTEK [Holtek Semiconductor Inc], HT1380A Datasheet - Page 6

• Manufacturer Part Number: HT1380A
• Description: Serial Timekeeper Chip
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

R/W Signal
The LSB of the Command Byte determines whether
the data in the register be read or be written to.
When it is set as ″0″ means that a write cycle is to take
place otherwise this chip will be set into the read mode.
A0~A2
A0 to A2 of the Command Byte is used to specify
which registers are to be accessed. There are eight
registers used to control the month data, etc., and each
of these registers have to be set as a write cycle in the
initial time.
Burst Mode
When the Command Byte is 10111110 (or 10111111),
the HT1380A/HT1381A is configured in burst mode.
In this mode the eight clock/calendar registers can
be written (or read) in series, starting with bit 0 of
register address 0 (see the timing on the next page).
Test Mode
When the Command Byte is set as 1001xxx1,
HT1380A/HT1381A is configured in test mode. The
test mode is used by Holtek only for testing purposes.
If used generally, unpredictable conditions may occur.
Write Protect Register
This register is used to prevent a write operation
to any other register. Data can be written into the
designated register only if the Write Protect signal
(WP) is set to logic 0. The Write Protect Register
should be set first before restarting the system or
before writing the new data to the system, and it
should set as logic 1 in the read cycle. The Write
Protect bit cannot be written to in the burst mode.
Clock HALT Bit
D7 of the Seconds Register is defined as the Clock
Halt Flag (CH).
When this bit is set to logic 1, the clock oscillator is
stopped and the chip goes into a low-power standby
mode. When this bit is written to logic 0, the clock
will start.
12-hour/24-hour Mode
The D7 of the hour register is defined as the 12-hour
or 24-hour mode select bit.
When this bit is in high level, the 12-hour mode is
selected otherwise it′s the 24-hour mode.
Rev. 1.00
6
AM-PM Mode
These are two functions for the D5 of the hour register
determined by the value D7 of the same register.
One is used in AM/PM selection on the 12-hour
mode. When D5 is logic 1, it is PM, otherwise it′s
AM. The other is used to set the second 10-hour bit
(20~23 hours) on the 24-hour mode.
Reset and Serial Clock Control
The REST pin is used to allow access data to the shift
register like a toggle switch. When the REST pin
is taken high, the built-in control logic is turned on
and the address/command sequence can access the
corresponding shift register. The REST pin is also
used to terminate either single-byte or burst mode
data format.
The input signal of SCLK is a sequence of a falling
edge followed by a rising edge and it is used to
synchronize the register data whether read or write.
For data input, the data must be read after the rising
edge of SCLK. The data on the I/O pin becomes
output mode after the falling edge of the SCLK. All
data transfer terminates if the REST pin is low and
the I/O pin goes to a high impedance state. The data
transfer is illustrated on the next page.
Data Input and Data Out
In writing a data byte with HT1380A/HT1381A, the
read/write should first set as R/W=0 in the Command
Byte and follow with the corresponding data register
on the rising edge of the next eight SCLK cycles.
Additional SCLK cycles are ignored. Data inputs are
entered starting with bit 0.
In reading a data on the register of HT1380A/
HT1381A, R/W=1 should first be entered as input.
The data bit outputs on the falling edge of the next
eight SCLK cycles. Note that the first data bit to be
transmitted on the first falling edge after the last bit of
the read command byte is written. Additional SCLK
cycles re-transmits the data bytes as long as REST
remains at high level. Data outputs are read starting
with bit 0.
Crystal Selection
A 32768Hz crystal can be directly connected to the
HT1380A/HT1381A on pins 2 and 3 which are the
crystal X1 and X2 pins. In order to ensure that the
desired frequency is achieved, it is recommended
to use a crystal with a capacitance of 9.0pF. It is
not recommended that additional load capacitors
are connected to the X1 and X2 pins. Refer to the
following page for the crystal specifications.
X 1
3 2 7 6 8 H z
HT1380A/HT1381A
June 15, 2012
X 2