HT1382_1105 HOLTEK [Holtek Semiconductor Inc], HT1382_1105 Datasheet - Page 18

• Manufacturer Part Number: HT1382_1105
• Description: I2C/3-Wire Real Time Clock
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Rev. 1.40
S
1 1 0 1 0 0 0 0
3-wire Serial Interface
Slave Address
S
S
Read Operation
R/W Signal
Burst Mode
Command Byte
1 1 0 1 0 0 0 0
1 1 0 1 0 0 0 1
Write
Slave Address
Slave Address
In this mode, the master reads the device data after setting the slave address. Following the R/W bit
(= 0 ) and the acknowledge bit, the register address (An) is written to the address W pointer. Next the
START condition and slave address are repeated followed by the R/W bit (= 1 ). The data which was
addressed is then transmitted. The address pointer is only incremented on reception of an acknowledge
clock. The device will then place the data at address An+1 on the bus. The master reads and
acknowledges the new byte and the address pointer is incremented to An+2 . After reaching the
memory location 0Fh, the pointer will be reset to 00h. This cycle of reading consecutive addresses will
continue until the master sends a STOP condition.
The device also support a 3-wire serial interface. The CE pin is used to identify the transmitted data.
The transmission is controlled by the active HIGH signal CE. Each data transfer is a byte, with the LSB
sent first. The first byte transmitted is the Command Byte.
For each data transfer, a Command Byte is initiated to specify which register is accessed. This is to
determine whether a read or write cycle is operational and whether a single byte or burst mode transfer
is to occur.
The LSB of the Command Byte determines whether the data in the register is to be read or be written
to. If it is 0 then this means that it is a write cycle. If it is 1 then this means that it is a read cycle.
When the Command Byte is 10111110 or 10111111, the device is configured in the burst mode. In this
mode, the address of registers from 00h to 0Fh can be written or read in series, starting with bit 0 of
register address 0.
ACK
Write
Read
Register Address(An)
ACK
ACK
Register Address(An)
ACK
Data(n)
Page Write Sequence
Read Sequence
Data(n)
ACK
ACK
18
P
ACK
Data(n+1)
I
2
C/3-Wire Real Time Clock
Data(n+1)
ACK
ACK
ACK
ACK
Data(n+x)
Data(n+x)
HT1382
May 27, 2011
ACK
ACK
P
P