CDK2308AITQ64 CADEKA [Cadeka Microcircuits LLC.], CDK2308AITQ64 Datasheet - Page 2

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CDK2308AITQ64

Manufacturer Part Number
CDK2308AITQ64
Description
Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
Manufacturer
CADEKA [Cadeka Microcircuits LLC.]
Datasheet
PRELIMINARY Data Sheet
Pin Configuration
TQFP-64
Pin Assignments
©2008 CADEKA Microcircuits LLC
DVDDCLK
DVSSCLK
24, 41, 58
25, 40, 57
1, 18, 23
3, 9, 12
Pin No.
CLKP
CLKN
4, 5, 8
10, 11
17, 64
6, 7
13
14
15
16
19
20
21
22
26
2
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
CLK_EXT_EN
Pin Name
IP0, IN0
IP1, IN1
CM_EXT
DV
OE_N_1
DV
D
DV
CLKN
PD_N
AV
CLKP
O
DV
AV
O
FRMT
NC
DDCLK
SSCLK
VDD
VSS
DD
DD
SS
SS
CDK2308
TQFP-64
Description
Digital and I/O-ring pre driver supply voltage, 1.8V
Common Mode voltage output
Analog supply voltage, 1.8V
Analog ground
Analog input Channel 0 (non-inverting, inverting)
Analog input Channel 1 (non-inverting, inverting)
Clock circuitry ground
Clock circuitry supply voltage, 1.8V
Clock input, non-inverting (Format: LVDS, PECL, CMOS/TTL, Sine Wave)
Clock input, inverting. For CMOS input on CLKP, bypass CLKN to ground with a 10nF capacitor
Digital circuitry ground
CLK_EXT signal enabled when low (zero). Tristate when high.
Data format selection. 0: Offset Binary, 1: Two's Complement
Full chip Power Down mode when Low. All digital outputs reset to zero.
Output Enable Channel 0. Tristate when high
I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V.
Ground for I/O ring
No Connect
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
N/C
N/C
N/C
CLK_EXT
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