ISPLSI1016E-100LJI LATTICE [Lattice Semiconductor], ISPLSI1016E-100LJI Datasheet
ISPLSI1016E-100LJI
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ISPLSI1016E-100LJI Summary of contents
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Features • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs — 96 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size ...
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Functional Block Diagram Figure 1. ispLSI 1016E Functional Block Diagram Generic Logic Blocks (GLBs) I I/O 1 I I I I/O 9 I/O ...
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Absolute Maximum Ratings Supply Voltage V ................................ -0.5 to +7.0V CC Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure 2) TEST ...
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External Timing Parameters 4 TEST 2 PARAMETER # COND Data Prop. Delay, 4PT Bypass, ORP Bypass pd1 t pd2 A 2 Data Prop. Delay, Worst Case Path Clk. Frequency with Int. Feedback max f ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 22 I/O Register Bypass iobp t 23 I/O Latch Delay iolat t 24 I/O Register Setup Time before Clock iosu t 25 I/O Register Hold Time after Clock ioh t 26 I/O ...
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Internal Timing Parameters 2 PARAMETER # Outputs t 49 Output Buffer Delay Output Slew Limited Delay Adder I/O Cell OE to Output Enabled oen t 52 I/O Cell OE to Output Disabled odis t ...
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Timing Model I/O Cell Ded. In #28 I/O Reg Bypass I/O Pin #22 (Input) Input Loading Register Q D RST #29, 31, 32 #59 # Reset Distribution Y1,2 Y0 GOE Derivations of ...
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Maximum GRP Delay vs GLB Loads Power Consumption Power consumption in the ispLSI 1016E device depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. Figure 3. Typical Device Power ...
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Pin Description PLCC NAME PIN NUMBERS I I/O 3 15, 16, 17, 18, 13, I I/O 7 19, 20, 21, 22, I I/O 11 25, 26, 27, 28, 19, 23, I I/O ...
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Pin Configurations ispLSI 1016E 44-Pin PLCC Pinout Diagram I/O 28 I/O 29 I/O 30 I/O 31 ispEN 1 SDI/ Pins have dual function capability. 2. Pins have dual function capability which is software selectable. ispLSI 1016E 44-Pin TQFP ...
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Part Number Description Device Family Device Number Speed 125 = 125 MHz fmax 100 = 100 MHz fmax MHz fmax ispLSI 1016E Ordering Information FAMILY fmax (MHz) tpd (ns) 125 125 100 ispLSI 100 84 84 FAMILY ...