A290011 AMICC [AMIC Technology], A290011 Datasheet

A290011

Manufacturer Part Number

A290011

Description

128K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory

Manufacturer

AMICC [AMIC Technology]

Datasheet

1.A290011.pdf (32 pages)

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Download datasheet (314Kb)

General Description

The A29001 is a 5.0 volt-only Flash memory organized as

131,072 bytes of 8 bits each. The A29001 offers the

function, but it is not available on A290011. The 128 Kbytes of

data are further divided into seven sectors for flexible sector

erase capability. The 8 bits of data appear on I/O

the addresses are input on A0 to A16. The A29001 is offered in

32-pin PLCC, TSOP, and PDIP packages. This device is

designed to be programmed in-system with the standard

system 5.0 volt VCC supply. Additional 12.0 volt VPP is not

required for in-system write or erase operations. However, the

A29001 can also be programmed in standard EPROM

programmers.

The A29001 has the first toggle bit, I/O

whether an Embedded Program or Erase is in progress, or it is

in the Erase Suspend. Besides the I/O

has a second toggle bit, I/O

addressed sector is being selected for erase. The A29001 also

offers the ability to program in the Erase Suspend mode. The

standard A29001 offers access times of 55, 70 and 90 ns

allowing high-speed microprocessors to operate without wait

states. To eliminate bus contention the device has separate

chip enable (

controls.

Preliminary

Features

n 5.0V

n Access times:

n Current:

n Flexible sector architecture

n Top or bottom boot block configurations available

n Embedded Erase Algorithms

PRELIMINARY

- 8 Kbyte/ 4 KbyteX2/ 16 Kbyte/ 32 KbyteX3 sectors

- Any combination of sectors can be erased

- Supports full chip erase

- Sector protection:

- 55/70/90 (max.)

- 20 mA typical active read current

- 30 mA typical program/erase current

- 1 A typical CMOS standby

- Embedded Erase algorithm will automatically erase the

- Embedded Program algorithm automatically writes and

A hardware method of protecting sectors to prevent

any inadvertent program or erase operations within

that sector

entire chip or any combination of designated sectors

and verify the erased sectors

verifies bytes at specified addresses

10% for read and write operations

), write enable ( WE ) and output enable (

(August, 2001, Version 0.3)

, to indicate whether the

toggle bit, the A29001

, which indicates

- I/O

RESET

while

)

The device requires only a single 5.0 volt power supply for both

read and write functions. Internally generated and regulated

voltages are provided for the program and erase operations.

The A29001 is entirely software command set compatible with

the JEDEC single-power-supply Flash standard. Commands

are

microprocessor write timings. Register contents serve as input

to an internal state-machine that controls the erase and

programming circuitry. Write cycles also internally latch

addresses and data needed for the programming and erase

operations. Reading data out of the device is similar to reading

from other Flash or EPROM devices.

Device programming occurs by writing the proper program

command sequence. This initiates the Embedded Program

algorithm - an internal algorithm that automatically times the

program pulse widths and verifies proper program margin.

Device erasure occurs by executing the proper erase

command sequence. This initiates the Embedded Erase

algorithm

preprograms the array (if it is not already programmed) before

executing the erase operation. During erase, the device

automatically times the erase pulse widths and verifies proper

erase margin.

n Typical 100,000 program/erase cycles per sector

n 20-year data retention at 125 C

n Compatible with JEDEC-standards

n Erase Suspend/Erase Resume

n Hardware reset pin (

n Package options

128K X 8 Bit CMOS 5.0 Volt-only,

- Reliable operation for the life of the system

- Pinout and software compatible with single-power-

- Superior inadvertent write protection

- Provides a software method of detecting completion of

- Suspends a sector erase operation to read data from,

- Hardware method to reset the device to reading array

- 32-pin P-DIP, PLCC, or TSOP (Forward type)

Data

supply Flash memory standard

data (not available on A290011)

written

program or erase operations

or program data to, a non-erasing sector, then

resumes the erase operation

A29001/290011 Series

Polling and toggle bits

Boot Sector Flash Memory

the

internal

command

RESET

AMIC Technology, Inc.

algorithm

)

that

using

automatically

standard

Related parts for A290011

A290011 Summary of contents

Page 1

... The A29001 is a 5.0 volt-only Flash memory organized as 131,072 bytes of 8 bits each. The A29001 offers the function, but it is not available on A290011. The 128 Kbytes of data are further divided into seven sectors for flexible sector erase capability. The 8 bits of data appear on I/O the addresses are input A16 ...

Page 2

... I A29001V/A290011V A29001/A290011 Series NC on A290011 5 A14 29 6 A13 A29001L/ 9 A11 25 A290011L A10 I A10 I ...

Page 3

... PGM Voltage Generator STB Timer Pin No. Description A0 - A16 Address Inputs - I/O Data Inputs/Outputs 0 7 Chip Enable CE Write Enable WE Output Enable OE Hardware Reset (N/A A290011) RESET VSS Ground VCC Power Supply 3 A29001/A290011 Series I/O - I/O 0 Input/Output Buffers Chip Enable Output Enable STB Data Latch Logic Y-Decoder ...

Page 4

... Legend Logic Low = Logic High = V IL Note: 1. See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information. 2. This function is not available on A290011. PRELIMINARY (August, 2001, Version 0.3) *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. ...

Page 5

... RESET pins ( 0.5V. (Note that this is a more restricted voltage range than V is held A290011) is held at VCC 0.5V. The device requires the standard access time (t If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ...

Page 6

... Sector A16 A15 SA0 0 0 SA1 0 1 SA2 1 0 SA3 1 1 SA4 1 1 SA5 1 1 SA6 1 1 Table 3. A29001/A290011 Bottom Boot Block Sector Address Table Sector A16 A15 SA0 0 0 SA1 0 0 SA2 0 0 SA3 0 0 SA4 0 1 SA5 1 0 SA6 1 ...

Page 7

... WE . The internal state machine is automatically reset to reading array data on the initial power-up. Temporary Sector Unprotect (N/A A290011) This feature allows temporary unprotection of previous protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET pin to V During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses ...

Page 8

... I/O sequence before Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" "1". 8 A29001/A290011 Series ID or I/O . See "Write "1", or cause the ...

Page 9

... Suspend command is valid. All other commands are ignored. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using I/O Operation Status" for information on these status bits. 9 A29001/A290011 Series , I I/O . See ...

Page 10

... See the appropriate Command Definitions table for erase command sequences. 2. See "I/O or I/O status bits, just A29001/A290011 Series START Write Erase Command Sequence Data Poll from System No Data = FFh ? Yes Erasure Completed : Sector Erase Timer" for more information. ...

Page 11

... Table 5. A29001/A290011 Command Definitions Command Sequence (Note 1) Read (Note 5) Reset (Note 6) Manufacturer ID Autoselect Top (Note 7) Device ID Bottom Continuation ID Sector Protect Verify (Note 8) Program Chip Erase Sector Erase Erase Suspend (Note 9) Erase Resume (Note 10) Legend Don't care RA = Address of the memory location to be read. ...

Page 12

... I/O , I/O , and I the A29001/A290011 to determine the status of a write operation. Table 6 and the following subsections describe the functions of these status bits. I/O offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. I/O : Data Polling ...

Page 13

... Under both these conditions, the system must issue the to control the read reset command to return the device to reading array data. I A29001/A290011 Series and I Toggle Bit II" explains the algorithm Toggle Bit I" subsection. Refer to the 6 vs. I/O ...

Page 14

... Notes : 1. Read toggle bit twice to determine whether or not Recheck toggle bit because it may stop toggling as I/O 14 A29001/A290011 Series START Read I/O -I Read I/O -I (Note 1) No Toggle Bit = Toggle ? ...

Page 15

... VCC+0.5V 2.0V PRELIMINARY (August, 2001, Version 0.3) Table 6. Write Operation Status I/O I (Note 1) Toggle I Toggle 1 No toggle Data Data Toggle I/O 7 20ns 20ns 20ns 20ns 20ns 20ns 15 A29001/A290011 Series I/O I/O I (Note 2) (Note 1) 0 N/A No toggle 0 1 Toggle 0 N/A Toggle Data Data Data 0 N/A N/A AMIC Technology, Inc. ...

Page 16

... Embedded Algorithm (program or erase progress Not 100% tested. 5. For CMOS mode only max at extended temperatures (> +85 C). CC3 6. RESET is not available on A290011. PRELIMINARY (August, 2001, Version 0.3) A29001/A290011 Series Test Description V = VSS to VCC. VCC = VCC Max IN VCC = VCC Max, ...

Page 17

... Test Setup Read Toggle and Data Polling on A29001 Addresses Stable t ACC OEH t CE High-Z Output Valid 17 A29001/A290011 Series Speed -55 -70 -90 Min Max Max Max Min Min Max ...

Page 18

... RESET Pulse Width RP t RESET High Time Before Read (See Note) RH Note: Not 100% tested. RESET Timings CE, OE RESET RESET Temporary Sector Unprotect (N/A on A290011) Parameter JEDEC Std t V Rise and Fall Time (See Note) VIDR ID RESET Setup Time for Temporary Sector t ...

Page 19

... See the "Erase and Programming Performance" section for more information. PRELIMINARY (August, 2001, Version 0.3) Description Min. Min. Min. Min. Min. Min. Min. low) Min. Min. Min. Min. Max. Typ. Typ. Min. 19 A29001/A290011 Series Speed Unit -55 -70 - ...

Page 20

... Note : PA = program addrss program data, Dout is the true data at the program address. PRELIMINARY (August, 2001, Version 0. WPH A0h PD 20 A29001/A290011 Series Read Status Data (last two cycles WHWH1 D Status OUT AMIC Technology, Inc. ...

Page 21

... Note : SA = Sector Address Valid Address for reading status data. PRELIMINARY (August, 2001, Version 0. 555h for chip erase WPH 55h 30h 10h for chip erase 21 A29001/A290011 Series Read Status Data WHWH2 In Complete Progress AMIC Technology, Inc. ...

Page 22

... Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle. PRELIMINARY (August, 2001, Version 0. Complement Complement Status Data Status Data 22 A29001/A290011 Series VA High-Z Valid Data True High-Z True Valid Data AMIC Technology, Inc. ...

Page 23

... PRELIMINARY (August, 2001, Version 0. Valid Status Valid Status (first read) (second read) . Illustration shows first two status cycle after command sequence, last status 6 23 A29001/A290011 Series VA VA Valid Status Valid Status (stop togging) AMIC Technology, Inc. ...

Page 24

... Erase Suspend Suspend Read Program and I/O in the section "Write Operation Statue" for 6 2 Description Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Typ. Typ. 24 A29001/A290011 Series Erase Resume Erase Erase Read Complete Speed -55 -70 - ...

Page 25

... DH PD for program 30 for sector erase 10 for chip erase Typ. (Note 1) Max. (Note 300 3.6 10.8 for further information A29001/A290011 Series PA I/O D OUT 7 = Complement of Data Input Array Data. 7 OUT Unit Comments sec Excludes 00h programming prior to erasure (Note 4) sec s ...

Page 26

... Parameter Minimum Pattern Data Retention Time PRELIMINARY (August, 2001, Version 0.3) Description Test Setup V Test Setup V Test Conditions 150 C 125 C 26 A29001/A290011 Series Min. Max. -1.0V VCC+1.0V -100 mA +100 mA -1.0V 12.5V RESET N/A on A290011. Typ. Max 7 8.5 12 OUT Typ. Max ...

Page 27

... Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Test Setup Device Under Test PRELIMINARY (August, 2001, Version 0.3) - 0.0 - 3.0 1.5 1.5 5 A29001/A290011 Series All others Unit 1 TTL gate 100 0.45 - 2.4 V 0.8, 2.0 V 0.8, 2.0 V Diodes = IN3064 or Equivalent AMIC Technology, Inc. ...

Page 28

... A290011TV-90 PRELIMINARY (August, 2001, Version 0.3) Active Read Program/Erase Current Current Typ. (mA) Typ. (mA A29001/A290011 Series Standby Current Package Typ 32Pin DIP 32Pin PLCC 1 32Pin TSOP 32Pin DIP 32Pin PLCC 1 32Pin TSOP 32Pin DIP 32Pin PLCC 1 32Pin TSOP AMIC Technology, Inc. ...

Page 29

... A290011UV-90 PRELIMINARY (August, 2001, Version 0.3) Active Read Program/Erase Current Current Typ. (mA) Typ. (mA A29001/A290011 Series Standby Current Package Typ 32Pin DIP 32Pin PLCC 1 32Pin TSOP 32Pin DIP 32Pin PLCC 1 32Pin TSOP 32Pin DIP 32Pin PLCC 1 32Pin TSOP AMIC Technology, Inc. ...

Page 30

... A - 0.100 - - 0.120 0.130 0.140 3.048 - A29001/A290011 Series unit: inches/ Nom Max - 5.334 - - 3.912 4.039 0.457 - 1.270 - 0.254 - 41.91 42.037 13.767 13.894 15.240 15.494 16.510 17.018 2.540 - 3 ...

Page 31

... D 0.390 0.410 0.430 9.91 E 0.585 0.590 0.595 14.86 D 0.485 0.490 0.495 12.32 E 0.075 0.090 0.095 1. 0.003 - & G are for PC Board surface mount pad pitch A29001/A290011 Series unit: inches/ Nom Max - 3. 2.80 2.93 0.71 0.81 0.46 0.54 0.254 0.35 13.97 14.05 11.43 11.51 1.27 1.42 12.95 13.46 10.41 10.92 14.99 15.11 12.45 12.57 2.29 2.41 - 0.075 - 10 AMIC Technology, Inc. ...

Page 32

... BSC 0.779 0.787 0.795 19.80 D 0.016 0.020 0.024 0.40 - 0.032 - - 0.020 - - - 0.003 - - A29001/A290011 Series unit: inches/ Detail "A" Nom Max - 1.20 - 0.15 1.00 1.05 0.22 0.27 - 0.20 18.40 18.50 8.00 8.10 0.50 BSC 20.00 20.20 0.50 0.60 0. 0. AMIC Technology, Inc. ...

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