F25L004A-100DIG ESMT [Elite Semiconductor Memory Technology Inc.], F25L004A-100DIG Datasheet
F25L004A-100DIG
Related parts for F25L004A-100DIG
F25L004A-100DIG Summary of contents
Page 1
... F25L004A –50PAIG 50MHz SOIC GENERAL DESCRIPTION The F25L004A is a 4Megabit, 3V only CMOS Serial Flash memory device. ESMT’s memory devices reliably store memory data even after 100,000 program and erase cycles. The F25L004A features a sector erase architecture. The device memory array is divided into 128 uniform sectors with 4K byte each ...
Page 2
... PIN CONFIGURATIONS 8-PIN SOIC VSS 4 8-PIN PDIP VSS 4 Elite Semiconductor Memory Technology Inc. Operation Temperature Condition -40 8 VDD HOLD 7 SCK VDD HOLD 7 SCK Publication Date: Jan. 2009 Revision: F25L004A ° C ° C ~85 1.3 2/33 ...
Page 3
... SCK. To activate the device when CE is low. The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. To temporality stop serial communication with SPI flash memory without resetting the device. To provide power. F25L004A ° C ~85 Publication Date: Jan. 2009 Revision: 1.3 3/33 ° ...
Page 4
... ESMT SECTOR STRUCTURE Table1 : F25L004A Sector Address Table Sector Size Sector (Kbytes) Block 127 4KB 112 4KB 111 4KB 4KB 95 4KB 4KB 79 4KB 4KB 63 4KB 4KB 47 4KB 4KB 31 4KB 4KB 15 4KB 4KB Elite Semiconductor Memory Technology Inc. ...
Page 5
... ESMT Table2 : F25L004A Block Protection Table Protection Level BP2 0 Upper 1/8 Upper 1/4 Upper 1/2 All Blocks All Blocks All Blocks All Blocks Block Protection (BP2, BP1, BP0) The Block-Protection (BP2, BP1, BP0) bits define the size of the memory area, as defined in Table2 to be software protected against any memory Write (Program or Erase) operations ...
Page 6
... ESMT FUNTIONAL BLOCK DIAGRAM Address Buffers and Latches CE Elite Semiconductor Memory Technology Inc. X-Decoder Y-Decoder I/O Butters Control Logic Data Latches Serial Interface SCK SO WP HOLD SI F25L004A Operation Temperature Condition -40 Flash and Publication Date: Jan. 2009 Revision: 1.3 ° C ° C ~85 6/33 ...
Page 7
... ctive Figure 1 : HOLD CONDITION WAVEFORM Write Protection F25L004A provides software Write protection. The Write Protect pin ( WP ) enables or disables the lockdown function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 2 for Block-Protection description ...
Page 8
... Chip-Erase instruction completion • Write-Status-Register instructions Elite Semiconductor Memory Technology Inc. Operation Temperature Condition -40 the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register. Function F25L004A ° C ~85 Default at Read/Write Power- ...
Page 9
... ESMT Instructions Instructions are used to Read, Write (Erase and Program), and configure the F25L004A. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, instructions, the Write-Enable (WREN) instruction must be executed first ...
Page 10
... The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A low for the duration of the Read cycle. See Figure 2 for the Read sequence ADD. ADD. ADD. MSB N D OUT MSB F25L004A Operation Temperature Condition - must remain active N+1 N+2 N+3 N+4 D ...
Page 11
... ADD. ADD. ADD. X MSB MSB F25L004A is reached, the address N+1 N+2 N+3 N ...
Page 12
... See Figure 4 for the Byte-Program sequence ADD. ADD. MSB HIGH IMPENANCE Operation Temperature Condition - Following the address, the data ADD MSB LSB Publication Date: Jan. 2009 Revision: 1.3 F25L004A ° C ° C ~85 12/33 ...
Page 13
... Elite Semiconductor Memory Technology Inc. Operation Temperature Condition - Following the addresses, two bytes of data is input sequentially FIGURE 6 : DISABLE SO AS HARDWARE DURING AAI PROGRAMMING F25L004A ° Refer to End-of-Write with A =1. CE must be driven The hardware end of write detection BP ...
Page 14
... ESMT FIGURE 7 : AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH HARDWARE END-OF-WRITE DETETION FIGURE 8 : AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH SOFTWARE END-OF-WRITE DETETION Elite Semiconductor Memory Technology Inc. F25L004A Operation Temperature Condition -40 Publication Date: Jan. 2009 Revision: 1.3 ° C ° ...
Page 15
... The user may poll the Busy bit in the software status register or wait TBE for the completion of the internal self-timed Block-Erase cycle. See Figure 9 for the Block-Erase sequence. Publication Date: Jan. 2009 Revision: F25L004A ° C ° C ~85 = Most Significant address) ...
Page 16
... Sector-Erase cycle. See Figure 10 for the Sector-Erase -A ]. Address bits sequence ADD. ADD. MSB MSB HIGH IMPENANCE F25L004A Operation Temperature Condition -40 = Most Significant address) are used to determine MS ), remaining address bits can be VIL ADD. Publication Date: Jan. 2009 Revision: 1.3 ° C ° ...
Page 17
... MSB Operation Temperature Condition -40 for the completion of the internal self-timed remain low until the status Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Status Register Out Publication Date: Jan. 2009 Revision: 1.3 F25L004A ° C ° C ~85 data is read. 17/33 ...
Page 18
... Figure 14 : WRITE DISABLE (WRDI) SEQUENCE Elite Semiconductor Memory Technology Inc MODE3 SCK MODE0 06 SI MSB HIGH IMPENANCE MODE3 SCK MODE0 04 SI MSB HIGH IMPENANCE SO F25L004A Operation Temperature Condition -40 Publication Date: Jan. 2009 Revision: 1.3 ° C ° C ~85 18/33 ...
Page 19
... BP0 ;BP1 and BP2 bits at the same time. See Table 3 for a summary description of WP and BPL functions 1011 12 13 1415 MSB HIGH IMPENANCE F25L004A Operation Temperature Condition -40 ) prior to the low-to-high transition of the IH STATUS REGISTER IN ...
Page 20
... HIGH IMPENANCE SO Figure 16 : Read-Electronic-Signature (RES) Elite Semiconductor Memory Technology Inc Bit7 MSB Operation Temperature Condition - Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Status Register Out Publication Date: Jan. 2009 Revision: 1.3 F25L004A ° C ° C ~85 20/33 ...
Page 21
... After that, a 16-bit device ID is shifted out on the SO pin. Byte1, 8CH, identifies the manufacturer as ESMT. Byte2, 20H, identifies the memory type as SPI Flash. Byte3, 13H, identifies the device as F25L004A. The instruction sequence is shown in Figure17. The JEDEC Read ID instruction is terminated by a low to high transition any time during data output other command is ...
Page 22
... ESMT Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as F25L004A and manufacturer as ESMT. This command is backward compatible to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in one design. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A Following the Read-ID instruction, the manufacturer’ ...
Page 23
... µ µ µ -0.2 DD Parameter Description F25L004A Operation Temperature Condition -40 Unit V °C Test Conditions /0.9 V @33 MHz, SO=open VIN =GND Max =GND Max OUT ...
Page 24
... F25L004A ° C ° ~85 Units Test Method Cycles JEDEC Standard A117 Years JEDEC Standard A103 mA JEDEC Standard 78 Units Max 100 MHz ...
Page 25
... V Elite Semiconductor Memory Technology Inc. Operation Temperature Condition -40 Limits Symbol Typ.(2) Max.(3) 90 200 300 100 100,000 - 20 - (min) DD F25L004A ° C ~85 Unit Cycles Years Publication Date: Jan. 2009 Revision: 1.3 25/33 ° C ...
Page 26
... ESMT FIGURE 19: SERIAL INPUT TIMING DIAGRAM FIGURE 20: SERIAL OUTPUT TIMING DIAGRAM Elite Semiconductor Memory Technology Inc. F25L004A Operation Temperature Condition -40 Publication Date: Jan. 2009 Revision: 1.3 ° C ° C ~85 26/33 ...
Page 27
... ESMT CE# SCK SO SI HOLD# FIGURE 21: HOLD TIMING DIAGRAM FIGURE 22: POWER-UP TIMING DIAGRAM Elite Semiconductor Memory Technology Inc. F25L004A Operation Temperature Condition -40 Publication Date: Jan. 2009 Revision: 1.3 ° C ° C ~85 27/33 ...
Page 28
... FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS FIGURE 24: A TEST LOAD EXAMPLE Elite Semiconductor Memory Technology Inc. 0.7VCC AC Measurement Level 0.3VCC Note : Input pulse rise and fall time are <5ns F25L004A Operation Temperature Condition -40 Output timing reference level 0.5VCC Publication Date: Jan. 2009 Revision: 1.3 ° C ° ...
Page 29
... Dimension in mm Dimension in inch Min Norm Max Min Norm 4.80 4.90 5.00 0.189 0.193 3.80 3.90 4.00 0.150 0.154 0.40 0.66 0.86 0.016 0.026 1.27 BSC 0.050 BSC 1.00 1.05 1.10 0.039 0.041 ° 0 ° 0 ° 8 --- Publication Date: Jan. 2009 Revision: 1.3 F25L004A ° C ° C ~85 L1 Max 0.197 0.157 0.034 0.043 ° 8 --- 29/33 ...
Page 30
... DETAIL "X" Dimension in mm Dimension in inch Min Norm Max Min Norm 7.70 7.90 8.10 0.303 0.311 5.18 5.28 5.38 0.204 0.208 0.50 0.65 0.80 0.020 0.026 1.27 BSC 0.050 BSC 1.27 1.37 1.47 0.050 0.054 ° 0 ° 0 ° 8 --- Publication Date: Jan. 2009 Revision: 1.3 F25L004A ° C ° C ~85 Max 0.319 0.212 0.032 0.058 ° 8 --- 30/33 ...
Page 31
... Dimension in inch Min Norm Max 0.21 0.015 0.125 0.130 0.135 0.355 0.365 0.400 0.300 BSC. 0.245 0.250 0.255 0.115 0.130 0.150 0.100 TYP. 0.335 0.355 0.375 0.018 TYP. 0.060 TYP Publication Date: Jan. 2009 Revision: 1.3 F25L004A ° C ° C ~85 31/33 ...
Page 32
... Correct the size of "L" in the packaging diagram of SOIC 150 mil 2.Add operating range table 2009.01.12 3.Delete the rating of Temperature Under Bias 4.Add the symbol for erase and byte programming time 5.Correct typo error 6.Modify headline F25L004A Operation Temperature Condition -40 Description Publication Date: Jan. 2009 Revision: 1.3 ° C ° ...
Page 33
... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Operation Temperature Condition -40 Important Notice F25L004A ° C ~85 Publication Date: Jan. 2009 Revision: 1 ...