A29010 AMICC [AMIC Technology], A29010 Datasheet - Page 13

• Manufacturer Part Number: A29010
• Description: 128K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory
• Manufacturer: AMICC [AMIC Technology]

I/O
Toggle Bit I on I/O
Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid after
the rising edge of the final
sequence (prior to the program or erase operation), and
during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address cause
I/O
control the read cycles.) When the operation is complete,
I/O
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O
approximately 100 s, then returns to reading array data. If
not all selected sectors are protected, the Embedded
Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected.
The system can use I/O
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O
device enters the Erase Suspend mode, I/O
toggling. However, the system must also use I/O
determine which sectors are erasing or erase-suspended.
Alternatively, the system can use I/O
on " I/O
If a program address falls within a protected sector, I/O
toggles for approximately 2 s after the program command
sequence is written, then returns to reading array data.
I/O
and stops toggling once the Embedded Program algorithm
is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O
algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram. The I/O
I/O
graphical form. See also the subsection on " I/O
Bit II".
I/O
The "Toggle Bit II" on I/O
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final
sequence.
I/O
those sectors that have been selected for erasure. (The
system may use either
cycles.) But I/O
actively
comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both status
PRELIMINARY
6
6
6
6
2
6
2
: Toggle Bit I
: Toggle Bit II
stops toggling.
also toggles during the erase-suspend-program mode,
figure shows the differences between I/O
to toggle. (The system may use either
toggles when the system reads at addresses within
7
:
erasing
Data
2
Polling").
cannot distinguish whether the sector is
(August, 2001, Version 0.3)
6
or
. Refer to Figure 4 for the toggle bit
6
indicates whether an Embedded
is
6
2
OE
, when used with I/O
and I/O
WE
erase-suspended.
WE
or
pulse in the command
CE
2
pulse in the command
together to determine
7
6
to control the read
(see the subsection
toggles. When the
6
OE
2
toggles for
6
and I/O
, indicates
I/O
or
2
: Toggle
6
6
CE
,
stops
2
2
6
vs.
by
to
to
in
6
13
bits are required for sector and mode information. Refer to
Table 6 to compare outputs for I/O
Figure 4 shows the toggle bit algorithm in flowchart form,
and the section " I/O
See also the " I/O
Toggle Bit Timings figure for the toggle bit timing diagram.
The I/O
and I/O
Reading Toggle Bits I/O
Refer to Figure 4 for the following discussion. Whenever
the system initially begins reading toggle bit status, it must
read I/O
a toggle bit is toggling. Typically, a system would note and
store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of
the toggle bit with the first. If the toggle bit is not toggling,
the device has completed the program or erase operation.
The system can read array data on I/O
following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of I/O
section on I/O
again whether the toggle bit is toggling, since the toggle bit
may have stopped toggling just as I/O
toggle bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is still
toggling, the device did not complete the operation
successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and I/O
gone high. The system may continue to monitor the toggle
bit and I/O
the status as described in the previous paragraph.
Alternatively, it may choose to perform other system tasks.
In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the
operation (top of Figure 4).
I/O
I/O
exceeded a specified internal pulse count limit. Under
these conditions I/O
condition that indicates the program or erase cycle was not
successfully completed.
The I/O
program a "1 "to a location that is previously programmed
to "0." Only an erase operation can change a "0" back to a
"1." Under this condition, the device halts the operation,
and when the operation has exceeded the timing limits,
I/O
Under both these conditions, the system must issue the
reset command to return the device to reading array data.
5
5
5
: Exceeded Timing Limits
produces a "1."
indicates whether the program or erase time has
6
2
5
7
in graphical form.
vs. I/O
failure condition may appear if the system tries to
- I/O
5
through successive read cycles, determining
0
5
). If it is, the system should then determine
at least twice in a row to determine whether
6
figure shows the differences between I/O
6
: Toggle Bit I" subsection. Refer to the
2
: Toggle Bit II" explains the algorithm.
5
produces a "1." This is a failure
AMIC Technology, Inc.
6
, I/O
2
2
A29010 Series
and I/O
5
5
went high. If the
7
6
is high (see the
.
- I/O
5
0
has not
on the
2