A29L400A AMICC [AMIC Technology], A29L400A Datasheet - Page 16

• Manufacturer Part Number: A29L400A
• Description: 512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
• Manufacturer: AMICC [AMIC Technology]

Write Operation Status
Several bits, I/O
the A29L400A to determine the status of a write operation.
Table 6 and the following subsections describe the functions
of these status bits. I/O
method for determining whether a program or erase
operation is complete or in progress. These three bits are
discussed first.
I/O
The
whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend.
valid after the rising edge of the final
program or erase command sequence.
During the Embedded Program algorithm, the device outputs
on I/O
This I/O
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O
The system must provide the program address to read valid
status information on I/O
protected sector,
approximately 2µs, then the device returns to reading array
data.
During the Embedded Erase algorithm,
produces a "0" on I/O
is complete, or if the device enters the Erase Suspend mode,
complement/true datum output described for the Embedded
Program algorithm: the erase function changes all the bits in
a sector to "1"; prior to this, the device outputs the
"complement," or "0." The system must provide an address
within any of the sectors selected for erasure to read valid
status information on I/O
After an erase command sequence is written, if all sectors
selected for erasing are protected,
active for approximately 100µs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
When the system detects I/O
complement to true data, it can read valid data at I/O
on the following read cycles. This is because I/O
change asynchronously with I/O
(
Embedded Algorithms) in the "AC Characteristics" section
illustrates this. Table 6 shows the outputs for
on I/O
PRELIMINARY
Data
OE
7
: Data Polling
Data
) is asserted low. The
7
Polling produces a "1" on I/O
7
. Figure 5 shows the
the complement of the datum programmed to I/O
7
status also applies to programming during Erase
Polling bit, I/O
2
, I/O
(July, 2005, Version 0.0)
Data
3
7
, I/O
. When the Embedded Erase algorithm
7
7
.
. If a program address falls within a
7
5
, I/O
, I/O
7
Polling on I/O
Data
, indicates to the host system
Data
6
6
, I/O
0
7
and RY/
- I/O
Polling algorithm.
7
has changed from the
.This is analogous to the
7,
Polling Timings (During
Data
RY/
6
while Output Enable
BY
WE
Polling on I/O
BY
7
Data
are provided in
is active for
Data
each offer a
pulse in the
Data
Polling is
Polling
7
Polling
7
- I/O
may
7
is
7
7
0
.
.
15
Note :
1. VA = Valid address for programming. During a sector
2. I/O
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
I/O
No
7
7
should be rechecked even if I/O
may change simultaneously with I/O
Figure 5. Data Polling Algorithm
Read I/O
Read I/O
Address = VA
Address = VA
I/O
I/O
I/O
START
7
7
AMIC Technology, Corp.
FAIL
= Data ?
= Data ?
5
= 1?
7
7
-I/O
Yes
- I/O
No
No
A29L400A Series
0
0
5
= "1" because
Yes
Yes
5
.
PASS