AS7C1028 ALSC [Alliance Semiconductor Corporation], AS7C1028 Datasheet - Page 2

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AS7C1028

Manufacturer Part Number
AS7C1028
Description
5V 256K X 4 CMOS SRAM (Common I/O)
Manufacturer
ALSC [Alliance Semiconductor Corporation]
Datasheet
12/5/06; V.1.0
Functional description
The AS7C1028 is a 5V high-performance CMOS 1,048,576-bit Static Random-Access Memory (SRAM) device organized
as 262,144 words × 4 bits. It is designed for memory applications requiring fast data access at low voltage, including
Pentium
operation without sacrificing performance or operating margins.
The device enters standby mode when CE is high. Equal address access and cycle times (t
enable access times (t
expansion with multiple-bank memory organizations.
A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is
written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The
chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write
enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0±0.5V supply. The AS7C1028 is packaged in
high volume industry standard packages.
Absolute maximum ratings
Note:
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Notes:
H = V
V
Other inputs
Voltage on V
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with V
DC current into outputs (low)
LC
= 0.2V, V
IH
, L = V
CE
TM
H
L
L
L
, PowerPC
HC
V
IL
HC
, x = Don’t care.
CC
= V
or V
relative to GND
CC
LC
Parameter
- 0.2V.
OE
.
TM
) of 6 ns are ideal for high-performance applications. The chip enable (CE) input permits easy memory
, and portable computing. Alliance’s advanced circuit design and process techniques permit 5.0V
WE
X
H
H
L
CC
applied
Alliance Memory
OE
X
H
X
L
Symbol
I
T
T
V
V
OUT
P
bias
stg
D
t1
t2
®
High Z
High Z
D
Data
Min
D
–0.5
–0.5
–55
–55
OUT
IN
AA
, t
RC
V
CC
, t
Max
+125
+125
+7.0
1.25
Output disable (I
50
Standby (I
WC
+ 0.5
) of 12 ns with output
Write (I
Read (I
Mode
P. 2 of 8
SB
CC
CC
AS7C1028
, I
)
)
SB1
CC
Unit
mA
)
o
o
W
)
V
V
C
C

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