MC92300CG Motorola, MC92300CG Datasheet
MC92300CG
Related parts for MC92300CG
MC92300CG Summary of contents
Page 1
... APLL VLCK 2 SR VTSTI[1:0] QVAL Figure 1. Viterbi Decoder Block Diagram Current Information@www.mot.com/ADC MC92300 DTVVIT BITCLK RESET_N VC0,VC1[2:0] VDCLK SYMCLK VTSTI[1:0] SR[2:0] SDA DSA[6:0] SCL Ordering Information Device Package MC92300CG Viterbi VO Core BIT- CLK Interface 7 SCL DSA SDA VO VLCK VFF VEF 128QFP 5/28/97 ...
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... Prior to outputting valid data the Viterbi decoder block must synchronize to the input data stream, i.e. remove any phase ambiguity in the received symbols and determine the punctured code rate transmitted MOTOROLA 2 The Viterbi block employs a method known as Syndrom Based Node Synchronization to achieve both I & Q symbol and punctured rate synchronization ...
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... VTSTI[1:0] - Test pins VTSTO - Test output RESET_ASYNC - Teset for Scan Test TEST_SE - Test pin for Scan Mode TEST_MODE - Test pin for Scan Mode MOTOROLA Device Test Pins: 51, 56-62, 105, 110-115, 120 (don’t connect these pins) NOT CONNECTED Pins: 27, 33, 34, 88-94, 99-102 MOTOROLA 3 ...
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... Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur ...