AT89LS53 ATMEL Corporation, AT89LS53 Datasheet
AT89LS53
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AT89LS53 Summary of contents
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... SPI serial interface conventional nonvol- atile memory programmer. By combining a versatile 8-bit CPU with downloadable Flash on a monolithic chip, the Atmel AT89LS53 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control appli- cations. ...
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... TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance inputs. Port 0 can also be configured to be the multiplexed low- order address/data bus during accesses to external pro- gram and data memory. In this mode, P0 has internal pul- lups. AT89LS53 4-250 33 P0.4 (AD4) 32 P0.5 (AD5 ...
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Block Diagram V CC GND RAM ADDR. REGISTER B REGISTER PSEN TIMING ALE/PROG INSTRUCTION AND REGISTER CONTROL RST WATCH OSC P0.0 - P0.7 PORT 0 DRIVERS PORT 0 RAM LATCH ACC TMP2 TMP1 ALU INTERRUPT, SERIAL ...
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... Port 3 pins that are externally being pulled low will source current (I ) because of the pullups. IL Port 3 also serves the functions of various special features of the AT89LS53, as shown in the following table. Port 3 also receives some control signals for Flash pro- gramming and verification. AT89LS53 4-252 ...
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... XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Table 1. AT89LS53 SFR Map and Reset Values 0F8H B 0F0H 00000000 0E8H ACC 0E0H 00000000 0D8H PSW 0D0H 00000000 T2CON T2MOD 0C8H ...
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... CP/RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX CP/RL2 when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. AT89LS53 4-254 SPI Registers Control and status bits for the Serial Periph- eral Interface are contained in registers SPCR (shown in Table 4) and SPSR (shown in Table 5) ...
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Dual Data Pointer Registers To facilitate accessing exter- nal data memory, two banks of 16 bit Data Pointer Regis- ters are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR WCON selects ...
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... SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and the SPIF bit) are cleared by reading the SPI status register with SPIF and WCOL set, and then accessing the SPI data register. AT89LS53 4-256 DORD ...
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... Bit 7 6 Data Memory - RAM The AT89LS53 implements 256 bytes of RAM. The upper 128 bytes of RAM occupy a parallel space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. ...
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... Timer 0 and 1 Timer 0 and Timer 1 in the AT89LS53 operate the same way as Timer 0 and Timer 1 in the AT89C51, AT89C52 and AT89C55. For further information, see the October 1995 Microcontroller Data Book, page 2-45, section titled, “Timer/Counters.” Timer 2 Timer bit Timer/Counter that can operate as either a timer or an event counter ...
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Figure 2 shows Timer 2 automatically counting up when DCEN = 0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit ...
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... Figure 3. Timer 2 Auto Reload Mode (DCEN = 1) Figure 4. Timer 2 in Baud Rate Generator Mode NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12 ÷ 2 OSC T2 PIN TRANSITION DETECTOR T2EX PIN AT89LS53 4-260 C/ TH2 CONTROL TR2 C/ RCAP2H RCAP2L EXF2 CONTROL EXEN2 TIMER 1 OVERFLOW ÷ 2 "0" ...
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Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the ...
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... SPI STATUS REGISTER AT89LS53 4-262 UART The UART in the AT89LS53 operates the same way as the UART in the AT89C51, AT89C52 and AT89C55. For fur- ther information, see the October 1995 Atmel Microcontrol- ler Data Book, page 2-49, section titled, “Serial Interface.” Serial Peripheral Interface ...
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The interconnection between master and slave CPUs with SPI is shown in the following figure. The SCK pin is the clock output in the master mode but is the clock input in the slave mode. Writing to the SPI data ...
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... SS (TO SLAVE) *Not defined but normally LSB of previously transmitted character Interrupts The AT89LS53 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10. ...
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Figure 11. Oscillator Connections Note: C1 for Crystals = for Ceramic Resonators Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively inverting amplifier that can be ...
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... Program Memory Lock Bits The AT89LS53 has three lock bits that can be left unpro- grammed (U) or can be programmed (P) to obtain the addi- tional features listed in the following table. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is pow- ...
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... Turn V power off. CC DATA Polling The AT89LS53 features DATA Polling to indicate the end of a write cycle. During a write cycle in the parallel or serial programming mode, an attempted read of the last byte writ- ten will result in the complement of the written datum on P0.7 (parallel mode), and on the MSB of the serial output byte on MISO (serial mode) ...
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... Serial Programming Algorithm To program and verify the AT89LS53 in the serial program- ming mode, the following sequence is recommended: 1. Power-up sequence: Apply power between V and GND pins. CC Set RST pin to “H” crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 12 MHz clock to XTAL1 pin and wait for at least 10 milliseconds ...
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Flash Parallel Programming Modes Mode Serial Prog. Modes Chip Erase Write (12K bytes) Memory Read (12K bytes) Memory Write Lock Bits: Bit - 1 Bit - 2 Bit - 3 Read Lock Bits: Bit - 1 Bit - 2 Bit ...
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... Figure 13. Programming the Flash Memory Figure 15. Verifying the Flash Memory AT89LS53 4-270 Figure 14. Flash Serial Downloading + ...
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Flash Programming and Verification Characteristics - Parallel Mode T = 0°C to 70° 5.0V 10 Symbol Parameter V Programming Enable Voltage PP I Programming Enable Current PP 1/t Oscillator Frequency CLCL t Address Setup to PROG ...
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... Flash Programming and Verification Waveforms - Parallel Mode Serial Downloading Waveforms SERIAL CLOCK INPUT SCK/P1.7 SERIAL DATA INPUT MOSI/P1.5 SERIAL DATA OUTPUT MISO/P1.6 AT89LS53 4-272 LSB MSB LSB MSB ...
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Absolute Maximum Ratings* Operating Temperature......................-55°C to +125°C Storage Temperature.........................-65°C to +150°C Voltage on Any Pin with Respect to Ground........................-1.0V to +7.0V Maximum Operating Voltage ................................6.6V DC Output Current .........................................15 Characteristics The values shown in this table are valid ...
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... Address Low AVWL t Data Valid to WR Transition QVWX t Data Valid to WR High QVWH t Data Hold After WR WHQX t RD Low to Address Float RLAZ High to ALE High WHLH AT89LS53 4-274 12MHz Oscillator Variable Oscillator Min Max Min 0 127 CLCL CLCL 48 ...
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External Program Memory Read Cycle External Data Memory Read Cycle 4-275 ...
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... External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL AT89LS53 4-276 V = 2.7V to 6.0V CC Min Max Units MHz ...
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Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for V Symbol Parameter t Serial Port Clock Cycle Time XLXL Output Data Setup to Clock t QVXH Rising Edge Output Data Hold After Clock ...
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... TYPICAL ICC (IDLE) at 25°C 4.8 4 2.4 m 1.6 A 0.8 0 (MHz) AT89LS53 4-278 TYPICAL ICC vs. VOLTAGE - POWER DOWN (85° Notes AT89LS53 4.0V 5.0V V VOLTAGE CC XTAL1 tied to GND for I (power down) CC Lock bits programmed 6.0V ...
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... Power Ordering Code (MHz) Supply 12 2.7V to 6.0V AT89LS53-12AC AT89LS53-12JC AT89LS53-12PC 2.7V to 6.0V AT89LS53-12AI AT89LS53-12JI AT89LS53-12PI 44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) 40P6 40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) Package 44A 44J 40P6 ...