AT89S51-24SC ATMEL Corporation, AT89S51-24SC Datasheet
AT89S51-24SC
Related parts for AT89S51-24SC
AT89S51-24SC Summary of contents
Page 1
... Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five- vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry ...
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... XTAL1 19 22 GND 20 21 TQFP (MOSI) P1.5 1 (MISO) P1.6 2 (SCK) P1.7 3 RST 4 (RXD) P3 (TXD) P3.1 7 (INT0) P3.2 8 (INT1) P3.3 9 (T0) P3.4 10 (T1) P3.5 11 AT89S51 2 VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8) 33 P0.4 (AD4) 32 P0.5 (AD5) 31 P0.6 (AD6) 30 P0.7 (AD7) 29 ...
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... RAM LATCH ACC TMP2 TMP1 ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSW PORT 3 LATCH PORT 3 DRIVERS P3.0 - P3.7 P2.0 - P2.7 PORT 2 DRIVERS FLASH LATCH PROGRAM STACK ADDRESS POINTER REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DUAL DPTR PROGRAM PORT 1 ISP LOGIC LATCH PORT PORT 1 DRIVERS P1.0 - P1.7 AT89S51 3 ...
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... Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Spe- cial Function Register. Port 2 also receives the high-order address bits and some control signals during Flash pro- gramming and verification. AT89S51 4 ) because of the internal pull-ups. IL Alternate Functions ...
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... As inputs, Port 3 pins that are externally being pulled low will source current (I Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the following table. Port Pin P3 ...
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... Note that not all of the addresses are occupied, and unoccupied addresses may not be imple- Registers mented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. Table 1. AT89S51 SFR Map and Reset Values 0F8H B 0F0H ...
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... ALE is active only during a MOVX or MOVC instruction Disable/Enable Reset-out DISRTO 0 Reset pin is driven High after WDT times out 1 Reset pin is input only Disable/Enable WDT in IDLE mode WDT continues to count in IDLE mode WDT halts counting in IDLE mode AT89S51 Reset Value = XXX00XX0B DISRTO – – DISALE ...
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... FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory. Data Memory The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space. ...
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... Description”. Timer 0 and 1 Timer 0 and Timer 1 in the AT89S51 operate the same way as Timer 0 and Timer 1 in the AT89C51. For further information on the timers’ operation, refer to the Atmel Web site (http://www.atmel.com). From the home page, select “Products”, then “Microcontrollers”, then “ ...
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... Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt. Symbol EA – – ES ET1 EX1 ET0 EX0 User software should never write 1s to reserved bits, because they may be used in future AT89 products. Figure 1. Interrupt Sources AT89S51 10 EA – – ES Position IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 ...
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... ± for Crystals = 40 pF ± for Ceramic Resonators NC EXTERNAL OSCILLATOR SIGNAL is restored to its normal operating level and must be held active long CC AT89S51 XTAL2 XTAL1 GND XTAL2 XTAL1 GND 11 ...
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... Table 5. Status of External Pins During Idle and Power-down Modes Mode Idle Idle Power-down Power-down Program The AT89S51 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the following table. Memory Lock Bits Table 6. Lock Bit Protection Modes 1 2 ...
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... XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than 1/16 of the crystal frequency. With a 33 MHz oscillator clock, the maximum SCK fre- quency is 2 MHz. Serial To program and verify the AT89S51 in the serial programming mode, the following sequence is recommended: Programming Algorithm 1 ...
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... Notes: 1. Each PROG pulse is 200 ns - 500 ns for Chip Erase. 2. Each PROG pulse is 200 ns - 500 ns for Write Code Data. 3. Each PROG pulse is 200 ns - 500 ns for Write Lock Bits. 4. RDY/BSY signal is output on P3.0 during programming don’t care. AT89S51 14 power off. CC ALE/ EA/ ...
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... XTAL1 RST GND PSEN AT89S51 ADDR. P1.0-P1.7 CC 0000H/FFFH P0 P2 A11 P2.6 P2.7 ALE SEE FLASH P3.3 PROGRAMMING MODES TABLE P3.6 P3.7 XTAL 2 EA 3-33 MHz XTAL1 RST GND PSEN AT89S51 V CC PGM DATA PROG RDY/ BSY PGM DATA (USE 10K PULLUPS ...
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... Data Float After ENABLE EHQZ t PROG High to BUSY Low GHBL t Byte Write Cycle Time WC Figure 6. Flash Programming and Verification Waveforms – Parallel Mode P1.0 - P1.7 P2.0 - P2.3 PORT 0 ALE/PROG EA/V PP P2.7 (ENABLE) P3.0 (RDY/BSY) AT89S51 16 PP PROGRAMMING ADDRESS DATA DVGL GHDX t t AVGL GHAX t t SHGL GHSL t ...
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... Figure 7. Flash Memory Serial Downloading Flash Programming and Verification Waveforms – Serial Mode Figure 8. Serial Programming Waveforms 2487B–MICRO–12/03 AT89S51 INSTRUCTION P1.5/MOSI INPUT P1.6/MISO DATA OUTPUT P1.7/SCK CLOCK IN XTAL2 3-33 MHz XTAL1 GND AT89S51 RST ...
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... For Page Read/Write, the data always starts from byte 0 to 255. After the command byte and upper address byte are latched, each byte thereafter is treated as data until all 256 bytes are shifted in/out. Then the next instruction will be ready to be decoded. AT89S51 18 Byte 2 ...
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... MOSI t t OVSH SCK t SHSL MISO = -40° 85° Min CLCL 8 t CLCL t CLCL 2 t CLCL 10 t SLSH SHOX t SLIV = 4.0 - 5.5V (Unless Otherwise Noted) CC Typ Max 500 400 CLCL AT89S51 Units MHz µs 19 ...
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... V OL than the listed test conditions. 2. Minimum V for Power-down is 2V. CC AT89S51 20 *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any ...
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... CLCL 203 4t -75 CLCL 23 t -30 CLCL 433 7t -130 CLCL 33 t -25 CLCL 0 43 123 t -25 CLCL AT89S51 Max Units 33 MHz -65 ns CLCL -60 ns CLCL ns t -25 ns CLCL ns 5t -80 ns CLCL ...
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... External Program Memory Read Cycle ALE PSEN PORT 0 PORT 2 External Data Memory Read Cycle ALE PSEN RD PORT FROM RI OR DPL PORT 2 AT89S51 22 t LHLL t t AVLL LLIV t LLPL t PLIV t PLAZ t LLAX t PXIX INSTR IN t AVIV A8 - A15 t LHLL t LLDV t RLRH ...
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... QVWX AVLL t QVWH FROM RI OR DPL DATA OUT t AVWL P2 A15 FROM DPH t t CHCX CLCH CLCX Min AT89S51 t WHLH t WHQX FROM PCL INSTR A15 FROM PCH t CHCX t CHCL t CLCL Max Units 33 MHz ...
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... IL (1) Float Waveforms Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V AT89S51 24 = 4.0V to 5.5V and Load Capacitance = 80 pF MHz Osc Min 1.0 ...
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... Ordering Information Speed Power (MHz) Supply Ordering Code 24 4.0V to 5.5V AT89S51-24AC AT89S51-24JC AT89S51-24PC AT89S51-24SC AT89S51-24AI AT89S51-24JI AT89S51-24PI AT89S51-24SI 33 4.5V to 5.5V AT89S51-33AC AT89S51-33JC AT89S51-33PC AT89S51-33SC 44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 42PS6 42-pin, 0.600" ...
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... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89S51 TITLE 44A, 44-lead Body Size, 1 ...
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... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 2487B–MICRO–12/03 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) AT89S51 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 4 ...
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... SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT89S51 28 D PIN 0º ~ 15º REF ...
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... TITLE 42PS6, 42-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP COMMON DIMENSIONS (Unit of Measure = mm) MIN SYMBOL NOM A – – A1 0.51 – D 36.70 – E 15.24 – E1 13.46 – B 0.38 – B1 0.76 – L 3.05 – C 0.20 – eB – – e 1.78 TYP DRAWING NO. AT89S51 MAX NOTE 4.83 – 36.96 Note 2 15.88 13.97 Note 2 0.56 1.27 3.43 0.30 18.55 11/6/03 REV. 42PS6 A 29 ...
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... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...