ADG732 Analog Devices, ADG732 Datasheet - Page 5

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ADG732

Manufacturer Part Number
ADG732
Description
16-/32- Channel/ 3.5 1.8 V to 5.5 V/ 2.5 V/ Analog Multiplexers
Manufacturer
Analog Devices
Datasheet

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REV. PrD
Figure 1 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive;
therefore, while
This input data is latched on the rising edge of
either as a dual 16-1 channel multiplexer or a differential 16 channel multiplexer. If a differential output is required, tie
TIMING CHARACTERISTICS
Parameter
t
t
t
t
t
t
NOTES
1
2
3
Specifications subject to change without notice.
1
2
3
4
5
6
See Figure 1.
All input signals are specified with tr =tf = 5ns (10% to 90% of V
Guaranteed by design and characterisation, not production tested.
and
together.
Limit at T
0
0
20
10
5
2
is held low, the latches are transparent and the switches respond to the address and enable inputs.
MIN
PRELIMINARY TECHNICAL DATA
, T
A0, A1, A2, A3, (A4)
MAX
CS
WR
EN
1,2, 3
DD
Figure 1. Timing Diagram
t
1
) and timed from a voltage level of (V
Units
ns min
ns min
ns min
ns min
ns min
ns min
. The ADG726 has two
t
3
–5–
t
5
Conditions/Comments
Time between
Address, Enable Setup Time
Address, Enable Hold Time
t
t
6
2
to
to
pulse width
t
4
IL
+ V
Setup Time
Hold Time
inputs. This enables the part to be used
IH
)/2.
cycles
ADG726/ADG732

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