LT3430 Linear Technology, LT3430 Datasheet - Page 20

• Manufacturer Part Number: LT3430
• Description: High Voltage/ 3A/ 200kHz Step-Down Switching Regulator
• Manufacturer: Linear Technology

LT3430
APPLICATIO S I FOR ATIO
calculation of the LT3430 die temperature. If a more
accurate die temperature is required, a measurement of
the SYNC pin resistance (to GND) can be used. The SYNC
pin resistance can be measured by forcing a voltage no
greater than 0.5V at the pin and monitoring the pin current
over temperature in an oven. This should be done with
minimal device power (low V
(V
ambient (oven) temperature.
Note: Some of the internal power dissipation in the IC, due
to BOOST pin voltage, can be transferred outside of the IC
to reduce junction temperature, by increasing the voltage
drop in the path of the boost diode D2 (see Figure 9). This
reduction of junction temperature inside the IC will allow
higher ambient temperature operation for a given set of
conditions. BOOST pin circuitry dissipates power given
by:
Typically V
equals V
considered almost equal, where:
Hence the equation used for boost circuitry power dissipa-
tion given in the previous Thermal Calculations section is
stated as:
Here it can be seen that boost power dissipation increases
as the square of V
V
the voltage drop in the path of D2. Care should be taken
that V
voltage required for full saturation of the internal power
switch. For output voltages of 5V, V
During switch turn on, V
C2 is dicharged by the BOOST pin. In the previous BOOST
Pin section, the value of C2 was designed for a 0.7V droop
in V
would still allow the minimum 3.3V for the boost function
20
C2
C
V
P
P
= 0V)) in order to calibrate SYNC pin resistance with
DISS
DISS BOOST
C2
C2
below V
C2
= V
= V
(
OUT
BOOST Pin
does not fall below the minimum 3.3V boost
OUT
DROOP
C2
. This is because diodes D1 and D2 can be
OUT
(the boost voltage across the capacitor C2)
– V
)
. Hence, an output voltage as low as 4V
to save power dissipation by increasing
FD2
OUT
V
U
OUT
– (–V
. It is possible, however, to reduce
V
C2
•
OUT
U
V
I
IN
will fall as the boost capacitor
FD1
SW
•
) = V
/
I
SW
36
V
IN
C2
IN
W
OUT
/
•
is approximately 5V.
36
and no switching
V
OUT
•
V
C
2
U
using the C2 capacitor calculated. If a target output voltage
of 12V is required, however, an excess of 8V is placed
across the boost capacitor which is not required for the
boost function but still dissipates additional power.
What is required is a voltage drop in the path of D2 to
achieve minimal power dissipation while still maintaining
minimum boost voltage across C2. A zener, D4, placed in
series with D2 (see Figure 9), drops voltage to C2.
Example : the BOOST pin power dissipation for a 20V input
to 12V output conversion at 2A is given by:
If a 7V zener D4 is placed in series with D2, then power
dissipation becomes :
For an FE package with thermal resistance of 45 C/W,
ambient temperature savings would be, T(ambient) sav-
ings = 0.233W • 45 C/W = 11 C. The 7V zener should be
sized for excess of 0.233W operaton. The tolerances of the
zener should be considered to ensure minimum V
exceeds 3.3V + V
V
IN
P
P
BOOST
BOOST
C3
Figure 9. BOOST Pin, Diode Selection
12 2 36 12
12 2 36 5
V
SHDN
SYNC
GND
IN
C
•
•
LT3430
BOOST
C
DROOP
R
C
20
20
/
/
BIAS
V
SW
C
.
FB
•
•
C
F
0 167
0 4
.
D1
C2
.
W
W
D2
D2
L1
R1
R2
3430 F09
D4
+
sn3430 3430is
C1
V
OUT
C2