LMC6681 National Semiconductor, LMC6681 Datasheet - Page 17

• Manufacturer Part Number: LMC6681
• Description: Low Voltage / Rail-To-Rail Input and Output CMOS
• Manufacturer: National Semiconductor

6.0 Powerdown
6.3 TEST CIRCUIT TO MEASURE t
The circuit used to measure the t
powerdown operation is a voltage follower with a load of
2 k
When the input to the powerdown pin is low, the LMC6681/
2/4 is on. Since the amplifier is connected in the voltage fol-
lower configuation, the output of the circuit is −1V. When the
6.4 t
The t
lay for device to power off) specs are guaranteed at a supply
voltage of 3V. The t
V
DC Threshold Characteristics table for the values for a logic
low and a logic high.
The guaranteed spec for t
that the signal to the V
µs). Note that the V
surements is 5 Hz. The LMC6681/2/4 is ideal for DC type ap-
plications where the powerdown pin is controlled by low fre-
quency signals.
When the LMC6681/2/4 is powered off, internal bias currents
are shutoff. There is a inherent latency in the circuit, and the
device has to power off for a certain period of time for the t
spec to apply. Refer to the figure below. t
time interval for which the device is in the powerdown mode.
Consider the case when the device has been powered off for
5 ms, and then the powerdown pin is pulled to a logic low.
From Figure 16 , at room temperature, the device powers on
after 500 µs.
PD
ON
applied in the specified range. Refer to the Powerdown
ON
as shown in Figure 14 .
and t
(time delay for device to power on) the t
OFF
(a) t
ON
PD
PD
OFF
and t
frequency for the t
pin can be as high as 5 kHz (1/200
ON
Measurement
(Continued)
OFF
is 200 µs. This does not mean
spec are independent of the
FIGURE 14. Test Circuit for t
ON
ON
, and t
AND t
PD OFF
ON
OFF
and t
DS012042-17
OFF
OFF
refers to the
during the
OFF
(time de-
mea-
ON
FIGURE 15.
17
ON
powerdown pin is pulled high, the amplifier shuts down, and
draws less than 1 µA/Amplifier. In this powerdown mode, the
output pin has high impedance, and the output of the circuit
is pulled to 0V. t
points of the trailing edges of the input waveform at the pow-
erdown pin, and the waveform at the output pin. Similarly,
the t
the leading edges of the input waveform at the powerdown
pin, and the waveform at the output pin.
and t
OFF
OFF
FIGURE 16. t
is specified as the time between the 50% points of
Measurements
t
PDOFF
(b) t
ON
in Powerdown Mode, V
ON
is specified as the time between the 50%
Measurement
ON
Delay Till Active-On after
DS012042-16
DS012042-29
S
DS012042-39
= 3V
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