LP2994M National Semiconductor, LP2994M Datasheet - Page 7

• Manufacturer Part Number: LP2994M
• Description: DDR Termination Regulator
• Manufacturer: National Semiconductor

Block Diagram
Description
The LP2994 is a linear bus termination regulator designed to
meet the JEDEC requirements of SSTL-2 and SSTL-3. The
output, V
regulating the output voltage equal to V
stage has been designed to maintain excellent load regula-
tion while preventing shoot through. The LP2994 also incor-
porates two distinct power rails which separates the analog
circuitry from the power output stage. This allows a split rail
approach to be utilized to decrease internal power dissipa-
tion. It also permits the LP2994 to provide a termination
solution for the next generation of DDR-SDRAM memory
(DDRII).
Series Stub Termination Logic (SSTL) was created to im-
prove signal integrity of the data transmission across the
memory bus. This termination scheme is essential to prevent
data error from signal reflections while transmitting at high
frequencies encountered with DDR-SDRAM. The most com-
mon form of termination is Class II single parallel termina-
tion. This involves one R
TT
is capable of sinking and sourcing current while
S
series resistor from the chipset to
DDQ
/ 2. The output
7
the memory and one R
for R
to scale the current requirements from the LP2994. This
implementation can be seen below in Figure 2 .
S
and R
FIGURE 2. SSTL Termination Scheme
T
are 25 Ohms, although these can be changed
T
termination resistor. Typical values
20045903
20045931
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