AT17N002 ATMEL Corporation, AT17N002 Datasheet

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AT17N002

Manufacturer Part Number
AT17N002
Description
FPGA Configuration Memory
Manufacturer
ATMEL Corporation
Datasheet

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Price
Part Number:
AT17N002-10TQC
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT17N002-10TQI
Manufacturer:
Atmel
Quantity:
10 000
Features
Description
The AT17N series FPGA Configuration EEPROM (Configurators) provide an easy-to-
use, cost-effective configuration memory for Field Programmable Gate Arrays. The
AT17N series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-lead
SOIC and 44-lead TQFP, see Table 1. The AT17N series Configurators uses a simple
serial-access procedure to configure one or more FPGA devices.
The AT17N series configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable and
factory programming.
Table 1. AT17N Series Packages
Note:
Package
8-lead LAP
8-lead PDIP
8-lead SOIC
20-lead SOIC
44-lead TQFP
EE Programmable 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and
4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field
Programmable Gate Arrays (FPGAs)
Available as a 3.3V (±10%) Commercial and Industrial Version
Simple Interface to SRAM FPGAs
Pin Compatible with Xilinx
Compatible with Xilinx Spartan
Mode
Very Low-power CMOS EEPROM Process
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP Packages for a
Specific Density
Low-power Standby Mode
High-reliability
– Endurance: Minimum 10 Write Cycles
– Data Retention: 20 Years at 85°C
1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-
lead SOIC package is not available for the AT17N512/010/002 devices, it is possi-
ble to use an 8-lead LAP package instead.
AT17N256
Yes
Yes
Yes
®
XC17SXXXA and XC17SXXXXL PROMs
®
Use 8-lead LAP
-II, Spartan-IIE and Spartan XL FPGAs in Master Serial
AT17N512/
AT17N010
Yes
Yes
Yes
(1)
Use 8-lead LAP
AT17N002
Yes
Yes
Yes
(1)
AT17N040
Yes
FPGA
Configuration
Memory
AT17N256
AT17N512
AT17N010
AT17N002
AT17N040
3.3V
System Support
Rev. 3020A–CNFG–05/03
1

Related parts for AT17N002

AT17N002 Summary of contents

Page 1

... LAP package instead. AT17N512/ AT17N010 AT17N002 Yes Yes Yes – (1) (1) Use 8-lead LAP Yes Yes – Yes FPGA Configuration Memory AT17N256 AT17N512 AT17N010 AT17N002 AT17N040 3.3V AT17N040 System Support – – – – Yes Rev. 3020A–CNFG–05/03 1 ...

Page 2

Pin Configuration AT17N256/512/010/002/040 2 8-lead LAP DATA 1 8 VCC CLK 2 7 VCC (SER_EN) RESET/ GND 8-lead SOIC DATA 1 8 VCC CLK 2 7 VCC (SER_EN) RESET/ ...

Page 3

AT17N256/512/010/002/040 44 TQFP ...

Page 4

Block Diagram SER_EN POWER ON RESET Device Description AT17N256/512/010/002/040 4 The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter- face directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and ...

Page 5

... Commercial and Industrial power supply pin. NC pins are No Connect pins, which are not internally bonded out to the die. DC pins are No Connect pins internally connected to the die not recommended to connect these pins to any external signal. AT17N256/512/010/002/040 AT17N002 LAP SOIC ...

Page 6

... Programming super voltages are generated inside the chip. The AT17N series configurators enter a low-power standby mode whenever CE is asserted High. In this mode, the AT17N256 configurator consumes less than 50 µA of current at 3.3V (100 µA for the AT17N512/010 and 200 µA for the AT17N002/040). (except during ISP). CC 3020A– ...

Page 7

Absolute Maximum Ratings* Operating Temperature.................................... -40°C to +85°C Storage Temperature ..................................... -65 °C to +150°C Voltage on Any Pin with Respect to Ground ..............................-0. Supply Voltage (V ) .......................................... 3.0V to +3.6V CC Maximum Soldering Temp. (10 sec. ...

Page 8

... Commercial 50 Industrial 100 AT17N256 Commercial Industrial Min Max Min Max AT17N512/ AT17N002/ AT17N010 AT17N040 Max Min Max Units V 2 0.8 0 0.8 2.4 0.4 0.4 2.4 0.4 0 -10 10 100 150 100 150 AT17N512/010/002/040 Commercial Industrial ...

Page 9

AC Characteristics CE RESET/OE CLK T CE DATA 3020A–CNFG–04/10/03 T SCE CAC AT17N256/512/010/002/040 T SCE T HOE HCE 9 ...

Page 10

... JC θ 150 JA (2) [°C/W] θ [°C/W] JC θ JA (2) [°C/W] θ [°C/W] – JC θ – JA (2) [°C/W] AT17N002 AT17N040 45 45 135.71 159.60 37 – 107 – – – – – – 17 – 62 3020A–CNFG–04/10/03 – – – – – – ...

Page 11

Figure 1. Ordering Code Voltage 3.3V 8CN4 8-lead mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOID Packages 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic ...

Page 12

... AT17N256-10NI AT17N256-10SI AT17N512-10CC AT17N512-10PC AT17N512-10SC AT17N512-10CI AT17N512-10PI AT17N512-10SI AT17N010-10CC AT17N010-10PC AT17N010-10SC AT17N010-10CI AT17N010-10PI AT17N010-10SI AT17N002-10CC AT17N002-10SC AT17N002-10TQC AT17N002-10CI AT17N002-10SI AT17N002-10TQI AT17N040-10TQC AT17N040-10TQI Package Operation Range 8P3 Commercial 8S1 (0°C to 70°C) 20S2 8P3 Industrial 8S1 (-40°C to 85°C) 20S2 8CN4 Commercial 8P3 (0° ...

Page 13

Packaging Information 8CN4 – LAP Marked Pin1 Indentifier E Top View 0.10 mm TYP Bottom View Note: 1. Metal Pad Dimensions. 2325 Orchard Parkway San Jose, CA 95131 R 3020A–CNFG–04/10/03 AT17N256/512/010/002/040 D Side View ...

Page 14

PDIP Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the ...

Page 15

SOIC 3 Top View e D Side View End View Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc. 2325 Orchard Parkway San Jose, CA ...

Page 16

SOIC Top View e D Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information. 2. Dimension "D" does not include mold Flash, protrusions or gate burrs. ...

Page 17

TQFP PIN 1 PIN 1 IDENTIFIER e C 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. ...

Page 18

... Available on web site Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...

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