XC68HC705F32 Motorola, XC68HC705F32 Datasheet - Page 105

• Manufacturer Part Number: XC68HC705F32
• Description: MICROCONTROLLER
• Manufacturer: Motorola

SPE — SPI system enable
When the SPE bit is set, port C pins 4, 5, 6, and 7 are dedicated to the SPI function.
DOD — Direction of data
This bit determines the direction of the data flow in or out of the serial shift register.
MSTR — Master/slave mode select
CPOL — Clock polarity
When the clock polarity bit is cleared and data is not being transferred, a steady state low value
is produced at the SCK pin of the master device. Conversely, if this bit is set, the SCK pin will idle
high. This bit is also used in conjunction with the clock phase control bit to produce the desired
clock-data relationship between master and slave. See
CPHA — Clock phase
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between
master and slave. The CPOL bit can be thought of simply as inserting an inverter in series with
the SCK line. The CPHA bit selects one of two fundamentally different clocking protocols. When
CPHA = 0, the shift clock is the logical OR of SCK and SS. As soon as SS goes low, the transaction
begins and the first edge on SCK invokes the first data sample. When CPHA = 1, the SS pin may
be thought of as a simple output enable control. Refer to
SPR1, SPR0 — SPI clock (SCK) rate select bits
If the device is a master, the two serial peripheral rate bits select one of four division ratios of the
E-clock to be used as SCK (See
MC68HC05F32
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
–
–
–
SPI system on.
SPI system off.
data is transferred LSB first.
data is transferred MSB first (default state).
master mode is selected.
slave mode is selected.
SERIAL PERIPHERAL INTERFACE
Table
10-1). These bits have no effect in slave mode.
Figure
Figure
10-1.
10-1.
MOTOROLA
TPG
10-7
10