ML4827CP-1 Micro Linear, ML4827CP-1 Datasheet - Page 11

• Manufacturer Part Number: ML4827CP-1
• Description: Fault-Protected PFC and PWM Controller Combo
• Manufacturer: Micro Linear

FUNCTIONAL DESCRIPTION
voltage for which the PWM output transistor must be
rated. Frequently, the design of the tranformer’s reset
winding, and/or of the output transistor’s snubbers or
clamps, require an additional voltage margin of 100V to
200V.
To put some numbers into the discussion, with a given
V
1. For
2. For
3. For
4. For
5. For
6. For
It is economically desirable to design for the lowest
meaningful voltage on the output MOSFET. It is
simultaneously necessary to design the circuit to operate
BUSS(MAX)
(1– )]} x 400V = 0.50/0.50 x 400V = 400V
0.64/0.36 x 400V = 711V
0.74/0.26 x 400V = 1138V
= 55%: V
= 60%: V
= 70%: V
= 50%: V
= 64% (Data Sheet Lower Limit Value): V
= 74% (Data Sheet Upper Limit Value): V
of 400V:
RESET
RESET
RESET
RESET
= 0.55/0.45 x 400V = 489V
= 0.60/0.40 x 400V = 600V
= 0.70/0.30 x 400V = 933V
= {[(1/f
Figure 3. ML4827- PWM Duty Cycle Clamp for Voltage-Made Operation
PWM
ERROR
PWM
AMP
) x ]/[(1/f
C RAMP2
R RAMP2
(Continued)
PWM
) x
RESET
RESET
R1
R FB1
R FB2
=
=
R2
V FB
RAMP2
V REF
V DC
PFC V BUSS
MAX =
at the lowest guaranteed value for , to ensure that the
magnetics will deliver full output power with any
individual ML4827. In actual operation, the choice of
capacitors and resistors. A tolerance on (R
C
achieve the desired result. This should be combined with
an external duty cycle clamp. This protects the PWM
circuitry against the condition in which the output has
been shorted, and the error amplifier output (V
otherwise be driven to its upper rail. One method which
works well when the PWM is used in voltage mode is to
limit the maximum input to the PWM feedback voltage
(V
the ML4827’s 7.5V V
charging time of the RAMP2 capacitor. This will be true
whether the RAMP2 capacitor is charged from V
is more commonly done in voltage-mode applications,
from the output of the PFC Stage (the “feedforward”
configuration). Figure 3 shows such a duty cycle clamp.
If the ML4827-2’s PWM is to be used in a current-mode
design, the PWM stage will require slope compensation.
This can be done by any of the standard industry
techniques. Note that the ramp to use for this slope
compensation is the voltage on RAMP1.
MIN
RAMP2
DC
R 2 V REF
R 1 + R 2
). If the voltage available to this pin is derived from
= 60% will allow some tolerance for the timing
) of ±2% is the simplest “brute force” way to
V RAMP2 (PEAK)
REF
, it will be in close ratio to the
RAMP2
ML4827
DC
REF
x
) would
, or, as
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