P87LPC762 Philips Semiconductors, P87LPC762 Datasheet - Page 16

• Manufacturer Part Number: P87LPC762
• Description: Low power/ low price/ low pin count 20 pin microcontroller with 2 kbyte OTP
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Checking ATN and DRDY
When a program detects ATN = 1, it should next check DRDY. If
DRDY = 1, then if it receives the last bit, it should capture the data
from RDAT (in I2DAT or I2CON). Next, if the next bit is to be sent, it
should be written to I2DAT. One way or another, it should clear
DRDY and then return to monitoring ATN. Note that if any of ARL,
2001 Oct 26
Low power, low price, low pin count (20 pin)
microcontroller with 2 kbyte OTP
I2CON
I2DAT
BIT
I2CON.7
I2CON.6
I2CON.5
I2CON.4
I2CON.3
I2CON.2
I2CON.1
I2CON.0
BIT
I2DAT.7
I2DAT.6–0
“
“
“
“
“
“
“
“
“
Address: D8h
Bit Addressable
Address: D9h
Not Bit Addressable
SYMBOL
SYMBOL
MASTER
WRITE
WRITE
READ
READ
DRDY
CSTR
RDAT
CARL
CSTP
XSTR
XSTP
RDAT
XDAT
IDLE
CDR
CXA
ATN
ARL
STR
STP
—
–
1
RDAT
RDAT
XDAT
CXA
7
7
FUNCTION
Read: the most recently received data bit.
Write: clears the transmit active flag.
Read: ATN = 1 if any of the flags DRDY, ARL, STR, or STP = 1.
Write: in the I
is needed again.
Read: Data Ready flag, set when there is a rising edge on SCL.
Write: writing a 1 to this bit clears the DRDY flag.
Read: Arbitration Loss flag, set when arbitration is lost while in the transmit mode.
Write: writing a 1 to this bit clears the CARL flag.
Read: Start flag, set when a start condition is detected at a master or non-idle slave.
Write: writing a 1 to this bit clears the STR flag.
Read: Stop flag, set when a stop condition is detected at a master or non-idle slave.
Write: writing a 1 to this bit clears the STP flag.
Read: indicates whether this device is currently as bus master.
Write: writing a 1 to this bit causes a repeated start condition to be generated.
Read: undefined.
Write: writing a 1 to this bit causes a stop condition to be generated.
FUNCTION
Read: the most recently received data bit, captured from SDA at every rising edge of SCL. Reading
I2DAT also clears DRDY and the Transmit Active state.
Write: sets the data for the next transmitted bit. Writing I2DAT also clears DRDY and sets the
Transmit Active state.
Unused.
IDLE
ATN
—
—
6
6
2
C slave mode, writing a 1 to this bit causes the I
Figure 6. I
DRDY
Figure 7. I
CDR
—
—
5
5
2
CARL
C Control Register (I2CON)
ARL
2
—
—
C Data Register (I2DAT)
4
4
13
CSTR
STR
—
—
3
3
STR, or STP is set, clearing DRDY will not release SCL to high, so
that the I
ATN = 1, and DRDY = 0, it should go on to examine ARL, STR,
and STP.
CSTP
STP
2
—
—
2
2
C will not go on to the next bit. If a program detects
MASTER
XSTR
—
—
1
1
2
C hardware to ignore the bus until it
XSTP
—
—
—
0
0
Reset Value: 81h
Reset Value: xxh
87LPC762
Preliminary data
SU01155
SU01156