COP8SA National Semiconductor, COP8SA Datasheet - Page 35

• Manufacturer Part Number: COP8SA
• Description: 8-Bit CMOS ROM Based and One-Time Programmable OTP Microcontroller with 1k to 4k Memory/ Power On Reset/ and Very Small Packaging
• Manufacturer: National Semiconductor

10.0 WATCHDOG/Clock Monitor
10.3 WATCHDOG AND CLOCK MONITOR SUMMARY
The following salient points regarding the WATCHDOG and
CLOCK MONITOR should be noted:
• Both the WATCHDOG and CLOCK MONITOR detector
• Following RESET, the WATCHDOG and CLOCK MONI-
• The WATCHDOG service window and CLOCK MONI-
• The initial WATCHDOG service must match the key data
• Subsequent WATCHDOG services must match all three
• The correct key data value cannot be read from the
• The WATCHDOG detector circuit is inhibited during both
• The CLOCK MONITOR detector circuit is active during
• With the single-pin R/C oscillator option selected and the
• With the crystal oscillator option selected, or with the
• The IDLE timer T0 is not initialized with external RESET.
• The user can sync in to the IDLE counter cycle with an
circuits are inhibited during RESET.
TOR are both enabled, with the WATCHDOG having the
maximum service window selected.
TOR enable/disable option can only be changed once,
during the initial WATCHDOG service following RESET.
value in the WATCHDOG Service register WDSVR in or-
der to avoid a WATCHDOG error.
data fields in WDSVR in order to avoid WATCHDOG er-
rors.
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all 0’s.
the HALT and IDLE modes.
both the HALT and IDLE modes. Consequently, the de-
vice inadvertently entering the HALT mode will be de-
tected as a CLOCK MONITOR error (provided that the
CLOCK MONITOR enable option has been selected by
the program).
CLKDLY bit reset, the WATCHDOG service window will
resume following HALT mode from where it left off before
entering the HALT mode.
single-pin R/C oscillator option selected and the CLKDLY
bit set, the WATCHDOG service window will be set to its
selected value from WDSVR following HALT. Conse-
quently, the WATCHDOG should not be serviced for at
least 256 instruction cycles following HALT, but must be
serviced within the selected window to avoid a WATCH-
DOG error.
IDLE counter (T0) interrupt or by monitoring the T0PND
flag. The T0PND flag is set whenever the twelfth bit of the
IDLE counter toggles (every 4096 instruction cycles). The
user is responsible for resetting the T0PND flag.
Don’t Care
Don’t Care
Mismatch
Match
Data
Key
Don’t Care
Don’t Care
Mismatch
Window
Match
Data
TABLE 8. WATCHDOG Service Actions
Don’t Care
Don’t Care
Mismatch
Monitor
Clock
Match
(Continued)
35
Valid Service: Restart Service Window
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
• A hardware WATCHDOG service occurs just as the de-
• Following RESET, the initial WATCHDOG service (where
• In order to RESET the device on the occurrence of a
10.4 DETECTION OF ILLEGAL CONDITIONS
The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.
Reading of undefined ROM gets zeroes. The opcode for
software interrupt is 00. If the program fetches instructions
from undefined ROM, this will force a software interrupt, thus
signaling that an illegal condition has occurred.
The subroutine stack grows down for each call (jump to sub-
routine), interrupt, or PUSH, and grows up for each return or
POP. The stack pointer is initialized to RAM location 06F Hex
during reset. Consequently, if there are more returns than
calls, the stack pointer will point to addresses 070 and 071
Hex (which are undefined RAM). Undefined RAM from ad-
dresses 070 to 07F (Segment 0), and all other segments
(i.e., Segments 4 … etc.) is read as all 1’s, which in turn will
cause the program to return to address 7FFF Hex. This is an
undefined ROM location and the instruction fetched (all 0’s)
from this location will generate a software interrupt signaling
an illegal condition.
Thus, the chip can detect the following illegal conditions:
1. Executing from undefined ROM
2. Over “POP”ing the stack by having more returns than
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restart-
ing (this recovery program is probably similar to that follow-
ing reset, but might not contain the same program initializa-
tion procedures). The recovery program should reset the
software interrupt pending bit using the RPND instruction.
vice exits the IDLE mode. Consequently, the WATCH-
DOG should not be serviced for at least 256 instruction
cycles following IDLE, but must be serviced within the se-
lected window to avoid a WATCHDOG error.
the service window and the CLOCK MONITOR enable/
disable must be selected) may be programmed any-
where within the maximum service window (65,536 in-
struction cycles) initialized by RESET. Note that this initial
WATCHDOG service may be programmed within the ini-
tial 256 instruction cycles without causing a WATCHDOG
error.
WATCH event, the user must connect the WDOUT pin
(G1) pin to the RESET external to the device. The weak
pull-up on the WDOUT pin is sufficient to provide the RE-
SET connection to V
On Reset and WATCHDOG.
calls.
Action
CC
for devices which use both Power
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