SP3203 Sipex, SP3203 Datasheet - Page 8

• Manufacturer Part Number: SP3203
• Description: 3V RS-232 Serial Transceiver with Logic Selector
• Manufacturer: Sipex

consists of a regulated dual charge pump that
provides output voltages of 5.5V regardless of
the input voltage (V
range. This is important to maintain compliant
RS-232 levels regardless of power supply
fluctuations.
The charge pump operates in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a of 5.5V, the charge
pump is enabled. If the output voltages exceed
a of 5.5V, the charge pump is disabled. This
oscillator controls the four phases of the voltage
shifting (Figure 12). A description of each phase
follows.
V
During this phase of the clock cycle, the positive
side of capacitors C
to V
charge in C
connected to V
capacitor C
Figure 10. Loopback Test Circuit Result at 120Kbps
(All Drivers Fully Loaded)
Rev. 6/25/03
Table 1. SHUTDOWN Truth Table.
(Note: When device in shutdown, the SP3203's charge pump is turned off
and V+ decays to V
are disabled as High Impendance).
R1 OUT
T1 OUT
S
SS
H
T1 IN
U
Charge Storage-Phase 1(Figure 13)
CC
T
0
D
1
1
2
3
. C
O
W
Ch1
Ch3
N
l +
1 –
2
CC.
is now 2 times V
is then switched to GND and the
5.00V Ch2 5.00V M 5.00µs Ch1
5.00V
is transferred to C
V- is pulled to ground and the transmitter outputs
CC
T
H
A
D
X
[
g i
c
O
E
, the voltage potential across
v i t
h
V
U
1
Z -
CC
e
C I
T
and C
: E
) over the +3.0V to +5.5V
T
T
T
S
T
P
2
3
R
H
are initially charged
A
2
X
g i
c
0
O
v i t
h
3
CC
U
Z -
e
2 –
T
.
. Since C
]
C
n I
0V
A
P
h
a
c
u
a
c
v i t
m
g r
v i t
p
2 +
e
e
e
is
8
SP3203
Figure 9. Loopback Test Circuit for RS-232 Driver Data
Transmission Rates
V
Phase two of the clock connects the negative
terminal of C
the positive terminal of C
transfers a negative generated voltage to C
This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage
to C
switched to V
connected to GND.
V
The third phase of the clock is identical to the
first phase — the charge transferred in C
Figure 11. Loopback Test Circuit result at 250Kbps
(All Drivers Fully Loaded)
R1 OUT
T1 OUT
SS
DD
T1 IN
3
Transfer-Phase 2 (Figure 14)
Charge Storage-Phase 3 (Figure 15)
TTL/CMOS
TTL/CMOS
, the positive side of capacitor C
OUTPUTS
INPUTS
1
2
3
C2
C1
C5
V
CC
+
+
+
Ch1
Ch3
0.1µF
0.1µF
0.1µF
2
5.00V Ch2 5.00V M 2.50µs Ch1
5.00V
CC
20
to the V
3
1
4
5
C1+
C1-
C2+
C2-
R
R
SHUTDOWN
T
T
and the negative side is
1
X
1
[
X
IN
OUT
IN
OUT
SP3203
+3V to +5V
V
GND
SS
© Copyright 2003 Sipex Corporation
CC
19
18
T
T
T
T
storage capacitor and
2
5KΩ
5KΩ
to GND. This
T
T
1
X
R
R
OUT
V L
OUT
1
X
V+
IN
IN
V-
+3V to +5.5V
2
6
12
1000pF
]
C3
C4
1
+
+
is
0V
0.1µF
0.1µF
1000pF
1
3
pro-
.