SP301 Burr-Brown, SP301 Datasheet
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SP301
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SP301 Summary of contents
Page 1
... CCD or CIS sensors. A Black Clamp and Correlated Double Samplers (CDS) are provided for CCD sensors. For CIS devices, the VSP3010 provides a single-ended sampler and a reference input. The VSP3010 is available in a 48-lead LQFP package and operates from +85 C with a single +5V supply. CK1 ...
Page 2
... A +4 1.6mA 0.5mA +2 +2 LOW OE = HIGH C = 15pF L Operating 4.7 3-Channel Mode 1-Channel Mode 3-Channel Mode 1-Channel Mode 0 2 VSP3010Y TYP MAX UNITS 12 Bits MHz MHz 3.5 Vp 1.75 V 800 V + 0.3 V DDA 1 2 LSB 0.3 0.75 LSB 12 Bits 0.3 LSBs rms 0.04 % FSR ...
Page 3
... NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “VSP3010Y/2K” will get a single 2000- piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. The information provided herein is believed to be reliable ...
Page 4
... Serial Data Input 22 SCLK DI Serial Data Clock Digital Power Supply, +5V DDD A/D Converter Output Enable ® VSP3010 VSP3010Y PIN DESIGNATOR 25 B0 (D0) LSB 26 B1 (D1 (D2 (D3 (D4 (D5) 31 ...
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... CK1 Pulse Width 15 CK2 Pulse Width 15 ADCCK Pulse Width 35 ADCCK Period 83 Sampling Delay Conversion Delay 22 Start Conversion Time CK1A CK1AP G1 B1 TYP MAX UNITS 250 100 ns VSP3010 ® ...
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... ADCCK Rising Edge to CK1 Rising Edge CK1SET t CK1 Rising Edge to ADCCK Falling Edge CK1ADC t ADDCK Falling Edge to CK2 Falling Edge ADDCK2 t CNV ADCCK Falling Edge to CK1 Rising Edge SET ® VSP3010 Pixel CK1BP t CK2B t CK12B CK1ADC ADCCK2 ...
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... PARAMETER MIN TYP MAX Address Setup Time 20 50 Data Setup Time 30 50 Readout Delay 20 Readout Hold Time 1 Parallel Ready Time TYP MAX UNITS 100 ns 200 ns ns VSP3010 t RH UNITS ® ...
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... Timing for A/D Output P/S OE DOUT ADCCK SYMBOL t ADC Output Enable Setup Time OES t OEW t OER ACKD t OEP ® VSP3010 Pixel ( Pixel ( CNV CNV ( (n) G ( ...
Page 9
... CK1 CK2 650 550 450 350 250 150 4.70 POWER DISSIPATION vs POWER SUPPLY (1-Channel Mode) 500 400 300 200 100 0 4.70 4.80 4.90 5.00 5.10 Power Supply Voltage (V) 9 POWER DISSIPATION vs POWER SUPPLY (3-Channel Mode) 4.80 4.90 5.00 5.10 5.20 Power Supply Voltage (V) 5.20 5.30 VSP3010 5.30 ® ...
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... THEORY OF OPERATION The VSP3010 can be operated in one of the following four modes: 3-Channel CCD Mode 3-Channel CIS Mode 1-Channel CCD Mode 1-Channel CIS Mode 3-CHANNEL CCD MODE In this mode, the VSP3010 can simultaneously process three output CCD signals. These signals are AC-coupled to the RINP, GINP, and BINP inputs ...
Page 11
... FIGURE 1. PGA Transfer Function Plot. CHOOSING AC INPUT COUPLING CAPACITORS The purpose of the input coupling capacitor is to isolate the DC output of the CCD array from affecting the VSP3010. The internal clamping circuitry restores the necessary DC component to the CCD output signal. The internal clamp voltage derived from the reference ...
Page 12
... VDRV, which is not con- nected to the analog supply pins. By adjusting the voltage on LOGIC ‘1’ VDRV, the digital output levels will vary respectively. CIS Mode Thus possible to operate the VSP3010 on a +5V analog V = 1.5V REF supply while interfacing the digital outputs to 3V logic. ...
Page 13
... Their effectiveness largely de- pends on the proximity to the individual supply pin. When the VSP3010 is powered on, it will be initialized as a 3-channel CCD, 1V internal (2V full scale) reference mode with analog gain of 1. This mode is commonly used for CCD scanner applications ...
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... IDT74FCT541T DRV V DDD V D GND TP0 A GND DDA V REF V A GND REFB CM REFT DDA V ® VSP3010 IDT74FCT541T OE DDD V SCLK SD P/S WRT RD D GND CK2 CK1 ADCCK STRT 14 ...
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... ADCCK CK2 SCLK 15 +5V TP0 37 36 (MSB) B11 (MSB) B11 35 B10 (A2) B10 (A2 (A1) B9 (A1 (A0) B8 (A0 (D7) B7 (D7 (D6) B6 (D6 (D5) B5 (D5 (D4) B4 (D4 (D3) B3 (D3 (D2) B2 (D2 (D1) B1 (D1) 25 (LSB) B0 (D0) (LSB) B0 (D0) 24 VSP3010 ® ...
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... BINP BINN 10 BINN 11 GND 12 V FIGURE 5. CIS Application Example. ® VSP3010 VSP3010 A A DDA STRT CK1 WRT SD ADCCK SCLK 16 +5V TP0 37 36 (MSB) B11 (MSB) B11 ...