A29040 AMIC Technology, A29040 Datasheet - Page 12

• Manufacturer Part Number: A29040
• Description: 512K X 8 Bit CMOS 5.0 Volt-only/ Uniform Sector Flash Memory
• Manufacturer: AMIC Technology

I/O
Toggle Bit I on I/O
or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I may
be read at any address, and is valid after the rising edge of the
final
program or erase operation), and during the sector erase time-
out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O
(The system may use either
cycles.) When the operation is complete, I/O
After an erase command sequence is written, if all sectors
selected
approximately 100 s, then returns to reading array data. If not
all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O
enters the Erase Suspend mode, I/O
the system must also use I/O
erasing or erase-suspended. Alternatively, the system can use
I/O
If a program address falls within a protected sector, I/O
toggles for approximately 2 s after the program command
sequence is written, then returns to reading array data.
I/O
and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for Toggle
Bit I on I/O
to the Toggle Bit Timings figure in the "AC Characteristics"
section for the timing diagram. The I/O
the differences between I/O
also the subsection on " I/O
I/O
The "Toggle Bit II" on I/O
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final
I/O
sectors that have been selected for erasure. (The system may
use either
cannot distinguish whether the sector is actively erasing or is
erase-suspended. I/O
device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information. Refer
to Table 5 to compare outputs for I/O
PRELIMINARY
7
6
2
6
2
: Toggle Bit I
(see the subsection on " I/O
: Toggle Bit II
toggles when the system reads at addresses within those
also toggles during the erase-suspend-program mode,
WE
for
6
pulse in the command sequence (prior to the
OE
. Refer to Figure 4 for the toggle bit algorithm, and
erasing
or
WE
6
(August, 2001, Version 0.1)
CE
indicates whether an Embedded Program
6
pulse in the command sequence.
, by comparison, indicates whether the
to control the read cycles.) But I/O
are
6
2
2
: Toggle Bit II".
2
, when used with I/O
and I/O
2
and I/O
OE
to determine which sectors are
protected,
7
:
Data
6
or
6
2
toggles. When the device
2
stops toggling. However,
6
and I/O
CE
together to determine
2
in graphical form. See
Polling").
vs. I/O
to control the read
I/O
6
6
stops toggling.
.
6
6
figure shows
toggles
6
6
, indicates
to toggle.
for
12
6
2
Figure 4 shows the toggle bit algorithm in flowchart form, and
the section " I/O
also the " I/O
Timings figure for the toggle bit timing diagram. The I/O
I/O
graphical form.
Reading Toggle Bits I/O
Refer to Figure 4 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O
bit is toggling. Typically, a system would note and store the
value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can
read array data on I/O
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O
on I/O
whether the toggle bit is toggling, since the toggle bit may have
stopped toggling just as I/O
longer toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the device did
not complete the operation successfully, and the system must
write the reset command to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O
system may continue to monitor the toggle bit and I/O
successive read cycles, determining the status as described in
the previous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine the
status of the operation (top of Figure 4).
I/O
I/O
exceeded a specified internal pulse count limit. Under these
conditions I/O
indicates the program or erase cycle was not successfully
completed.
The I/O
program a "1 "to a location that is previously programmed to
"0." Only an erase operation can change a "0" back to a "1."
Under this condition, the device halts the operation, and when
the operation has exceeded the timing limits, I/O
"1."
Under both these conditions, the system must issue the reset
command to return the device to reading array data.
6
7
5
5
: Exceeded Timing Limits
- I/O
figure shows the differences between I/O
indicates whether the program or erase time has
5
). If it is, the system should then determine again
5
0
failure condition may appear if the system tries to
at least twice in a row to determine whether a toggle
6
: Toggle Bit I" subsection. Refer to the Toggle Bit
5
produces a "1." This is a failure condition that
2
: Toggle Bit II" explains the algorithm. See
7
- I/O
AMIC Technology, Inc.
0
6
5
, I/O
on the following read cycle.
A29040A Series
went high. If the toggle bit is no
2
5
5
is high (see the section
has not gone high. The
2
5
and I/O
produces a
5
through
2
6
vs.
in