AK4520 Asahi Kasei Microsystems, AK4520 Datasheet - Page 7
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AK4520
Manufacturer Part Number
AK4520
Description
100dB 20Bit Stereo ADC & DAC
Manufacturer
Asahi Kasei Microsystems
Datasheet
1.AK4520.pdf
(19 pages)
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ASAHI KASEI
Notes: 11.If the duty cycle of LRCK changes larger than 5 to 50%, the AK4520A is reset by the internal phase
0163-E-00
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout=-100uA)
Low-Level Output Voltage (Iout=100uA)
Input Leakage Current
Master Clock Timing
LRCK Frequency
Serial Interface Timing
Reset Timing
(Ta=25 C; VA,VD=2.7 5.5V)
(Ta=25 C; VA,VD=2.7 5.5V; C
SCLK Period
SCLK Pulse Width Low
LRCK Edge to SCLK " "
SCLK " " to LRCK Edge
LRCK to SDTO(MSB)
SCLK " " to SDTO
SDTI Hold Time
SDTI Setup Time
PWAD & PWDA Pulse Width
PWAD " " to SDTO valid
Duty Cycle
12.SCLK rising edge must not occur at the same time as LRCK edge.
13.These cycles are the number of LRCK rising from PWAD rising.
circuit automatically.
Pulse Width High
Parameter
Parameter
Pulse Width Low
Pulse Width High
384fs:
Pulse Width Low
Pulse Width High
256fs:
VD=2.7-3.6V
VD=4.5-5.5V
(Note 11 )
(Note 13 )
(Note 12 )
(Note 12 )
L
=20pF)
SWITCHING CHARACTERISTICS
DIGITAL CHARACTERISTICS
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fs
fs
tSCK
tSCKL
tSCKH
tLRS
tSLR
tLRM
tSSD
tSDH
tSDS
tPW
tPWV
Symbol
- 7 -
Symbol
VOH
VOL
VIH
VIL
Iin
4.096
6.144
289.4
min
120
120
150
70%VD
27
27
20
20
16
16
45
30
30
40
40
VD-0.5
min
-
-
-
44.1
44.1
516
typ
typ
-
-
-
-
30%VD
max
13.824
20.736
±10
0.5
max
100
100
-
-
50
54
55
[AK4520A]
Units
1997/3
uA
MHz
MHz
V
V
V
V
Unit
kHz
1/fs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%