AK4116VF Asahi Kasei Microsystems, AK4116VF Datasheet
AK4116VF
Related parts for AK4116VF
AK4116VF Summary of contents
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ASAHI KASEI The AK4116 is a low power S/PDIF AES/EBU receiver supporting resolution up to 24-bit. The integrated channel status decoder supports both consumer and professional modes. The AK4116 can automatically detect a Non-PCM bit stream. Combining the AK4116 with ...
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ASAHI KASEI Block Diagram AVSS RX0 DVDD DVSS AC-3/MPEG Detect MS0156-E-02 AVDD R XTI X'tal Clock Oscillator Recovery DAIF Decoder Error & Q-subcode STATUS buffer Detect INT0 INT1 - 2 - [AK4116] XTO Clock MCKO Generator LRCK Audio BICK I/F ...
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... ASAHI KASEI Ordering Guide -40 ~ +85 °C AK4116VF Pin Layout RX0 DVDD DVSS XTI XTO MS0156-E-02 20pin QFN (0.5mm pitch Top View [AK4116] INT1 CSN CCLK CDTI CDTO 2004/04 ...
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ASAHI KASEI No. Pin Name I/O 1 RX0 I 2 DVDD - 3 DVSS - 4 XTI I 5 XTO O 6 LRCK O 7 BICK O 8 SDTO O 9 DAUX I 10 MCKO O 11 CDTO O 12 ...
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ASAHI KASEI (AVSS, DVSS=0V; Note 2) Parameter Power Supplies: Analog Digital |AVSS-DVSS| Input Current (Any pins except supplies) Input Voltage (Except RX0, RX1 pins) (RX0, RX1 pins) Ambient Temperature (Power applied) Storage Temperature Note 2. All voltages with respect to ...
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ASAHI KASEI (Ta=25°C; AVDD, DVDD=2.7~3.6V; C Parameter Master Clock Timing Crystal Resonator Frequency External Clock Frequency Duty Cycle MCKO Output Frequency Duty Cycle PLL Clock Recover Frequency (RX0) LRCK Timing Frequency PLL mode X’tal mode External Clock mode Duty Cycle ...
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ASAHI KASEI Timing Diagram XTI MCKO LRCK LRCK tMBLR BICK SDTO DAUX MS0156-E-02 1/fECLK tECLKH tECLKL dECLK = tECLKH x fECLK x 100 1/fMCK tMCKH tMCKL dMCK = tMCKH x fMCK x 100 1/fs tLRH tLRL dLCK = tLRH x ...
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ASAHI KASEI CSN CCLK CDTI CDTO Figure 3. WRITE/READ Command Input Timing CSN CCLK CDTI D3 CDTO CSN CCLK CDTI A1 CDTO MS0156-E-02 tCSS tCCK tCCKL tCCKH tCDH tCDS C1 C0 R/W Hi-Z tCSH Hi-Z Figure 4. ...
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ASAHI KASEI CSN CCLK CDTI CDTO D3 PDN MS0156-E- Figure 6. READ Data Input Timing 2 tPW Figure 7. Power Down & Reset Timing - 9 - [AK4116] tCSW VIH VIL tCSH VIH VIL VIH VIL tCCZ ...
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ASAHI KASEI Non-PCM (AC-3, MPEG, etc.) and DTS-CD Bitstream Detection The AK4116 has a Non-PCM steam auto-detection function. When the 32-bit mode Non-PCM preamble based on Dolby “AC-3 Data Stream in IEC60958 Interface” is detected, the NPCM bit goes to ...
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ASAHI KASEI Master Clock Output The AK4116 has a master clock output pin, MCKO. In PLL mode, PLL lock range 48kHz and the MCKO frequency is fixed to 256fs. In the X’tal mode, XCKS1-0 bits select the ...
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ASAHI KASEI Clock Source The following circuits are available to feed a clock into the XTI pin of AK4116. 1) X’tal mode The X’tal with proper value should be connected between XTI and XTO pins. Note: External capacitance depends on ...
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ASAHI KASEI Sampling Frequency and Pre-emphasis Detection The AK4116 has two methods for detecting the sample frequency: 1) Clock comparison between recovered clock and the X’tal oscillator FS3-0 bits indicate the detected RX input frequency referred to X’tal frequency. XTL1-0 ...
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ASAHI KASEI System Reset and Power-Down The AK4116 has a full power-down mode for all circuits that is activated by the PDN pin, and a partial power-down mode activated by the PWN bit. The RSTN bit initializes the internal registers ...
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ASAHI KASEI Biphase signal input circuit 75Ω Coax Figure 11. Consumer Input Circuit (Coaxial Input) Note: When using a coaxial input, if the coupling level to this input from the next RX input line pattern exceeds 50mV, incorrect operation may ...
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ASAHI KASEI Q-subcode buffers The AK4116 has a Q-subcode buffer for CD application. The AK4116 takes Q-subcode into registers under the following conditions: 1) The sync word (S0,S1) is consists of least 16 “0”s. 2) The start bit is “1”. ...
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ASAHI KASEI Interrupt Handling There are eight events which cause the INT1-0 pins to go “H”. 1. UNLCK: PLL unlock state detect “1” when the PLL loses lock. The AK4116 loses lock when the distance between two preambles is not ...
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ASAHI KASEI Interrupt (UNLCK, PAR,..) INT0 pin INT1 pin Register (PAR,STC, CINT,QINT) Register (others) Command MCKO,BICK,LRCK (UNLCK) MCKO,BICK,LRCK (except UNLCK) SDTO (UNLCK) SDTO (PAR error) SDTO (others) MS0156-E-02 (Interrupt) Hold ”1” Free Run (fs: around 20kHz) Previous Data Figure 16. ...
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ASAHI KASEI Release Muting Figure 17. Interrupt Handling Sequence Example 1 MS0156-E-02 PDN pin ="L" to "H" Initialize Read 05H INT0/1 pin ="H" No Yes Mute DAC output Read 05H (Each Error Handling) Read 05H (Resets registers) No INT0/1 pin ...
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ASAHI KASEI Figure 18. Interrupt Handling Sequence Example (for Q/CINT) MS0156-E-02 PDN pin ="L" to "H" Initialize Read 05H INT1 pin ="H" No Yes Read 05H and Detect QSUB= “1” (Read Q-buffer) No New data QCRC = “0” Yes No ...
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ASAHI KASEI Audio Serial Interface Format The DIF2-0 bits can select six serial data formats as shown in Table 7. In all formats, the serial data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge ...
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ASAHI KASEI LRCK BICK (64fs) SDTO 15:MSB, 0:LSB LRCK BICK (64fs SDTO 23:MSB, 0:LSB LRCK BICK (64fs SDTO 23:MSB, 0:LSB LRCK 0 ...
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ASAHI KASEI Serial Control Interface The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO. The data on this interface consists of Chip address (2bits, C1-0 are fixed to “00”), ...
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ASAHI KASEI Register Map Addr Register Name 00H Power Down Control 01H Clock Control 02H Input/Output Control 03H INT0 MASK MULK0 04H INT1 MASK MULK1 05H Receiver status 0 UNLCK 06H Receiver status 1 07H Receiver status 2 08H RX ...
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ASAHI KASEI Register Definitions Addr Register Name 00H Power Down Control R/W Default RSTN: Timing Reset & Register Initialize 0: Reset & Initialize (except RSTN, PWN, XTL1-0 and EXCK bits) 1: Normal Operation (Default) PWN: Power-Down for Clock Recovery Part ...
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ASAHI KASEI Addr Register Name 02H Format Control R/W Default DIF2-0: Audio Data Format Control (Table 7; Default: 100) EFH1-0: INT0 Pin Hold Count Select 00: 512 LRCK 10: 2048 LRCK CS12: Channel Status Select 0: Channel 1 (Default) 1: ...
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ASAHI KASEI Addr Register Name 03H INT0 MASK R/W Default MQIT0: Mask Enable for QINT bit MCIT0: Mask Enable for CINT bit MSTC0: Mask Enable for STC bit MAUD0: Mask Enable for AUDION bit MV0: Mask Enable for V bit ...
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ASAHI KASEI Addr Register Name D7 05H Receiver status 0 UNLCK R/W RD Default 0 QINT: Q-subcode Buffer Interrupt 0: No change This bit goes to “1” when Q-subcode stored in register addresses 11H to 1AH is updated. CINT: Channel ...
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ASAHI KASEI Addr Register Name 06H Receiver status 1 R/W Default FS3-0: Sampling Frequency Detection (Table 4) PEM: Pre-emphasis Detect 0: OFF This bit is made by encoding the channel status bits. NPCM: Non-PCM Bit Stream Auto Detection 0: No ...
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ASAHI KASEI Addr Register Name 08H RX Channel Status Byte 0 09H RX Channel Status Byte 1 0AH RX Channel Status Byte 2 0BH RX Channel Status Byte 3 0CH RX Channel Status Byte 4 R/W Default CR39-0: Receiver Channel ...
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ASAHI KASEI Burst Preambles in non-PCM Bitstreams preamble Aux Preamble word Length of field Pa 16 bits Pb 16 bits Pc 16 bits Pd 16 bits MS0156-E-02 sub-frame of IEC60958 ...
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ASAHI KASEI Bits of Pc value contents 0-4 data type 0 NULL data 1 Dolby AC-3 data 2 reserved 3 PAUSE 4 MPEG-1 Layer1 data 5 MPEG-1 Layer2 or 3 data or MPEG-2 without extension 6 MPEG-2 data with extension ...
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ASAHI KASEI Non-PCM Bitstream timing 1) When Non-PCM preamble does not arrive within 4096 frames, PDN pin Bit stream AUTO bit Pc Register “0” Pd Register “0” 2) When Non-PCM bitstream stops (when MULK0=0), INT0 ...
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ASAHI KASEI Figure system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. 3.3V Supply S/PDIF (see Figure 11-13) 10u 0.1u + 3.3V Supply C (see ...
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ASAHI KASEI 20pin QFN (Unit: mm) 4.20 ± 0.10 4.00 ± 0.05 C0.7 0.22 ± 0.05 0.05 0.60 ± 0.10 Note: The black parts of back package should be open. Material & Lead finish Package molding compound: Lead frame material: ...
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... ASAHI KASEI • These products and their specifications are subject to change without notice. any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • ...