ZL50120 Zarlink, ZL50120 Datasheet
ZL50120
Manufacturer Part Number
ZL50120
Description
32 / 64 / 128 Channel CESoP Processors
Manufacturer
Zarlink
Datasheet
1.ZL50120.pdf
(95 pages)
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Features
General
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Circuit Emulation Services
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Customer Side TDM Interfaces
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Circuit Emulation Services over Packet (CESoP)
transport for MPLS, IP and Ethernet networks
On chip timing & synchronization recovery across
a packet network
On chip dual reference Stratum 3 DPLL
Grooming capability for Nx64 Kbps trunking
Fully compatible with Zarlink's ZL50110, ZL50111
and ZL50114 CESoP processors
Complies with ITU-T recommendation Y.1413
Complies with IETF PWE3 draft standards
CESoPSN and SAToP
Complies with CESoP Implementation
Agreements from MEF 8 and MFA 8.0.0
Structured, synchronous CESoP with clock
recovery
Unstructured, asynchronous CESoP with integral
per-stream clock recovery
Up to 4 T1/E1, 1 J2, 1 T3/E3, or 1 STS-1 ports
H.110, H-MVIP, ST-BUS backplane
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Figure 1 - ZL50115/16/17/18/19/20 High Level Overview
(LIU, Framer, Backplane)
Stratum 3 DPLL
Dual Reference
Per Port DCO for
Clock Recovery
(Jitter Buffer Compensation for 128 ms of Packet Delay Variation)
Interface
TDM
Zarlink Semiconductor Inc.
On Chip Packet Memory
32-bit Motorola compatible
DMA for signaling packets
Multi-Protocol
IPv4, IPv6, MPLS,
ECID, VLAN, User
Host Processor
PW, RTP, UDP,
Defined, Others
Processing
1
Interface
Packet
Engine
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Customer Side Packet Interfaces
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(may also be used as a second provider side packet
interface)
Provider Side Packet Interfaces
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ZL50115GAG 324 Ball PBGA trays, bake & dry pack
ZL50116GAG 324 Ball PBGA trays, bake & dry pack
ZL50117GAG 324 Ball PBGA trays, bake & dry pack
ZL50118GAG 324 Ball PBGA trays, bake & dry pack
ZL50119GAG 324 Ball PBGA trays, bake & dry pack
ZL50120GAG 324 Ball PBGA trays, bake & dry pack
Up to 128 bi-directional 64 Kbps channels
Direct connection to LIUs, framers, backplanes
100 Mbps MII Fast Ethernet (ZL50118/19/20 only)
100 Mbps MII Fast Ethernet or 1000 Mbps
GMII/TBI Gigabit Ethernet
32, 64 and 128 Channel CESoP
(MII, GMII, TBI)
Ordering Information
Interface
Packet
MAC
Dual
JTAG
-40°C to +85°C
ZL50115/16/17/18/19/20
Processors
Data Sheet
April 2005
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