AM79C202 Legerity, AM79C202 Datasheet - Page 8

• Manufacturer Part Number: AM79C202
• Description: (AM79C202 / AM79212) PCM CODEC
• Manufacturer: Legerity

8
ASLAC Device
Pin Names
Pin Names
I/O1, I/O2
C2–C1
AGND
DGND
VREF
IBAT
VTX
DCL
IDIF
IDC
IAB
DD
DU
FS
I1
Input/Output
Output
Output
Output
Output
Type
Type
Input
Input
Input
Input
Input
Input
Input
Input
Gnd
Gnd
Analog Reference. This voltage is provided by the ASLAC device and is used by the
ASLIC device for internal reference purposes. All analog input and output signals inter-
facing to the ASLAC device are referenced to this pin. Nominally set to 2.1 V.
Four-Wire Transmit Signal. The voltage between this pin and VREF is a scaled version of
the AC component of the voltage sensed between the SA and SB pins. One end of the
two-wire input impedance programming network connects to VTX. The voltage at VTX
swings positive and negative about VREF.
Analog (Quiet) Ground. VREF is referenced to this ground.
ASLIC Device Control. These ternary logic output pins are dedicated to controlling the op-
erating state of the ASLIC device. The levels of these outputs are logic High, logic Low,
and High impedance.
GCI Clock. This input controls the clocking of the GCI data and is also used as the master
clock for the CODEC and DSP. 2.048 MHz or 4.096 MHz clock frequencies can be used.
In either case, the GCI bit rate is always 2.048 MHz.
Downstream GCI Data. Downstream data is received serially on the DD port every 125
µs at the DCL rate.
Digital Ground. This is the digital ground return.
Upstream GCI Data. Upstream data is sent serially on the DU pin every 125 µs at the DCL
rate. DU is high impedance between bursts. This pin is an open drain output.
Frame Sync. The Frame Sync signal is an 8 kHz pulse that identifies the beginning of a
GCI frame. The ASLAC device references the timing of back-plane data transfer to this
input. The back-plane data bit rate must be synchronized to DCL.
Control Port. This input port is TTL compatible and can be used to monitor an external
TTL compatible device. The logic state of this pin appears in the I1 bit (bit 2) of the up-
stream C/I channel.
Loop Voltage Sense. The IAB pin is a current summing node referenced to VREF. An ex-
ternal resistor (RAB) is connected between this pin and the VDC pin of the ASLIC device.
In normal operation, current flows out of this pin. When the ASLIC device is in thermal
shutdown, current will be forced into this pin.
Battery Voltage Sense. The IBAT pin is a current summing node referenced to AGND and
receives a current that is proportional to the system battery voltage. A sense resistor/ca-
pacitor network is connected between the VBAT pin of the ASLIC device and the IBAT
pin.
DC Loop Control Current. The IDC output supplies a current to the ASLIC device for pro-
portional control of the DC loop current flowing through the subscriber loop.
Longitudinal Sense. IDIF is a current input pin and is fed by the IDIF pin of the ASLIC de-
vice. The current in this pin is used by the ASLAC device for supervisory and diagnostic
functions. The IDIF pin has an internal input resistance so an external longitudinal noise-
filter capacitor can be connected.
Control Ports. These control lines are TTL compatible and each can be programmed as
an input or an output. When programmed as inputs, they can monitor external, TTL-com-
patible logic circuits. In the output mode, these pins are controlled by the I/O1 and I/O2
bits in the downstream C/I channel. In the output or input modes, the logic state of these
pins appears in the I/O1 and I/O2 bits of the upstream C/I channel. When programmed
as outputs, they can control an external logic device or they can be connected to pin C3,
C4, or C5 of the ASLIC device to control test relay drivers RY1OUT, RY2OUT, and
RY3OUT.
Am79212/Am79C202 Data Sheet
Description
Description