AT52BC6402A-70CI ATMEL Corporation, AT52BC6402A-70CI Datasheet - Page 33

• Manufacturer Part Number: AT52BC6402A-70CI
• Description: 64 MBIT FLASH 16 MBIT PSRAM
• Manufacturer: ATMEL Corporation

Write Cycle 1 (PSWE Controlled)
Write Cycle 2 (CS1 Controlled)
Notes:
3441B–STKD–11/04
1. A write occurs during the overlap of a low CS1, a low PSWE, and a low UB or LB.
2. t
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be
4. If the CS1, LB and UB low transition occur simultaneously with the PSWE low transition or after the PSWE transition, out-
5. PSOE is continuously low (PSOE = V
6. Q (data out) is the invalid data.
7. Q (data out) is the read data of the next address.
8. The t
9. CS1 in high for the standby, low for active.
10. Do not input data to the I/O pins while they are in the output state.
DATA OUT
DATA OUT
ADDRESS
ADDRESS
DATA IN
DATA IN
applied.
puts remain in a high impedance state.
levels.
WR
UB, LB
PSWE
PSWE
UB,LB
is measured from the earlier of CS1 or PSWE going high to the end of write cycle.
CS2
CS1
CS2
CS1
WHZ
is defined as the time at which the outputs achieves the high impedance state. It is not referenced to output voltage
HIGH-Z
HIGH-Z
HIGH-Z
V
V
IH
IH
t
AS
t
AS
(1),(4),(5),(9),(10)
(1),(4),(5),(9),(10)
IL
).
t
WHZ
t
t
AW
AW
(3)(8)
t
CW
t
t
WC
t
CW
WC
t
t
BW
BW
t
WP
t
WP
DATA VALID
t
DW
t
DW
DATA VALID
t
t
WR
WR
t
OW
t
t
AT52BC6402A(T)
DH
DH
(2)
(2)
(6)
(7)
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