K4S161622D-TC/L10 Samsung semiconductor, K4S161622D-TC/L10 Datasheet - Page 40
K4S161622D-TC/L10
Manufacturer Part Number
K4S161622D-TC/L10
Description
512K x 16Bit x 2 Banks Synchronous DRAM
Manufacturer
Samsung semiconductor
Datasheet
1.K4S161622D-TCL10.pdf
(41 pages)
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CLOCK
K4S161622D
ADDR
DQM
CKE
RAS
CAS
WE
DQ
CS
Mode Register Set Cycle
* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
*Note :
0
1
1. CS, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
MODE REGISTER SET CYCLE
MRS
Key
*Note 2
*Note 3
*Note 1
2
HIGH
Hi-Z
3
Command
New
Ra
4
5
6
7
8
Auto Refresh Cycle
0
9
Auto Refresh
1
10
2
11
HIGH
3
12
Hi-Z
13
4
5
tRC
14
6
15
CMOS SDRAM
16
7
17
8
New Command
9
18
: Don't care
10
19
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