UCN5818F Allegro, UCN5818F Datasheet

UCN5818F

Manufacturer Part Number

UCN5818F

Description

BiMOS II 32-BIT SERIAL-INPUT / LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS

Manufacturer

Allegro

Datasheet

1.UCN5818F.pdf (8 pages)

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OUT

Logic Supply Voltage, V

Driver Supply Voltage, V

Continuous Output Current,

Input Voltage Range,

Package Power Dissipation, P

Operating Temperature Range,

Storage Temperature Range,

* Derate at rate of 28 mW/°C above T

† Derate at rate of 22 mW/°C above T

Caution: CMOS devices have input static

protection but are susceptible to damage when

exposed to extremely high static electrical

charges.

(UCN5818AF) ............................ 3.5 W*

(UCN5818EPF) ......................... 2.7 W†

OUT

................................. -20

............................... -55

SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS

....................... -0.3 V to V

......................... -40 mA to +15 mA

.................... 15 V

................... 60 V

C to +150

OUT

C to +85

= +25°C

BiMOS II 32-BIT SERIAL-INPUT, LATCHED

+ 0.3 V

Dwg. PP-059-2

OUT

5818-F

UCN5818AF and UCN5818EPF smart power BiMOS II drivers combine

CMOS shift registers, data latches, and control circuitry, with bipolar high-

speed sourcing outputs and DMOS active pull-down circuitry. The high-

speed shift register and data latches allow direct interfacing with microproces-

sor LSI-based systems. A CMOS serial data output enables cascade connec-

tions in applications requiring additional drive lines. Both devices feature

60 V and -40 mA output ratings, allowing them to be used in many other

peripheral power driver applications.

improved data entry rates. With a 5 V supply, it will operate to at least 3.3

MHz. At 12 V, higher speeds are possible. Use of these devices with TTL

may require the use of appropriate pull-up resistors to ensure an input logic

high. All devices can be operated over the ambient temperature range of -

20°C to +85°C. The UCN5818AF is supplied in a 40-pin plastic dual in-line

package with 0.600" (15.24 mm) row spacing. A copper lead frame, reduced

supply current requirement, and low output saturation voltage permits

operation with minimum junction temperature rise. The ‘A’ package allows

all 32 outputs to be operated at -25 mA continuously over the operating

temperature range.

in a 44-lead plastic chip carrier (quad pack) for surface mounting on solder

lands with 0.050" (1.27 mm) centers. The PLCC allows -25 mA continuous

operation of all outputs simultaneously at ambient temperatures to 60°C.

Similar devices are available as the UCN5810AF/LWF (10 bits), UCN5811A

(12 bits), and UCN5812AF/EPF (20 bits).

I 60 V Source Outputs

I High-Speed Source Drivers

I To 3.3 MHz Data Input Rate

I Low-Output Saturation Voltages

I Active DMOS Pull-Downs

Always order by complete part number, e.g., UCN5818EPF .

Designed primarily for use with vacuum-fluorescent displays, the

These smart power drivers have been designed with BiMOS II logic for

For high-density packaging applications, the UCN5818EPF is furnished

I Low-Power CMOS Logic

I Reduced Supply Current

I Improved Replacements for

and Latches

Requirements

SN75518N/FN

Related parts for UCN5818F

UCN5818F Summary of contents

Page 1

BiMOS II 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS OUT OUT OUT OUT 19 ° Logic Supply Voltage, V .................... Driver Supply ...

... OUT OUT 150 Dwg. GP-025A 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1988, 2000 Allegro MicroSystems, Inc SERIAL-PARALLEL SHIFT REGISTER LATCHES MOS BIPOLAR V BB OUT OUT Dwg. EP-010-5 ...

Page 3

... Output Fall Time t f Output Rise Time t r Negative current is defined as coming out of (sourcing) the specified device terminal. * Operation at a clock frequency greater than the specified minimum value is possible but not warranteed. www.allegromicro.com WITH ACTIVE-DMOS PULL-DOWNS ° Test Conditions +70°C OUT ...

Page 4

SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS CLOCK DATA STROBE BLANKING OUT N ° A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time ...

Page 5

... MAX 0.39 MIN NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. 4. Supplied in standard sticks/tubes of 9 devices. www.allegromicro.com WITH ACTIVE-DMOS PULL-DOWNS 0.070 0.100 0.030 2.095 BSC 1.980 0.022 ...

Page 6

SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS 0.319 0.291 0.021 0.013 0.319 0.291 0.050 BSC 8.10 7.39 0.533 0.331 8.10 7.39 1.27 BSC NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead ...

Page 7

... WITH ACTIVE-DMOS PULL-DOWNS The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current ...

Page 8

SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS * Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. † Complete part ...

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