AS7C251MFT32A ALSC [Alliance Semiconductor Corporation], AS7C251MFT32A Datasheet

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AS7C251MFT32A

Manufacturer Part Number
AS7C251MFT32A
Description
2.5V 1M x 32/36 Flow-through synchronous SRAM
Manufacturer
ALSC [Alliance Semiconductor Corporation]
Datasheet
January 2005
Features
• Organization: 1,048,576 words × 32 or 36 bits
• Fast clock to data access: 7.5/8.5/10 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
Logic block diagram
Selection guide
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
1/17/05, v 1.2
A[19:0]
ADSC
ADSP
GWE
CLK
BWE
ADV
2.5V 1M × 32/36 Flow-through synchronous SRAM
BW
BW
BW
BW
CE0
CE1
CE2
OE
ZZ
a
d
c
b
Power
down
Alliance Semiconductor
20
D
D
CE
CLK
CLK
D
CLK
D
CLK
D
CLK
D
CE
CLK
D
CLK
CLK
CE
CLR
Byte write
Byte write
Byte write
Byte write
registers
registers
registers
registers
register
325
130
Enable
-75
8.5
7.5
Address
register
register
delay
90
Enable
DQ
DQ
DQ
DQ
d
c
b
a
Q
Burst logic
Q
Q
Q
Q
Q
Q
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
LBO
Q0
Q1
20
®
2
18
20
2
CLK
OE
32/36
registers
300
130
-85
Output
8.5
10
90
4
1M × 32/36
Memory
DQ[a:d]
array
32/36
32/36
CLK
registers
Input
Copyright © Alliance Semiconductor. All rights reserved.
AS7C251MFT32A
AS7C251MFT36A
275
130
-10
10
12
90
1 of 19
Units
mA
mA
mA
ns
ns

Related parts for AS7C251MFT32A

AS7C251MFT32A Summary of contents

Page 1

... Byte write registers CLK D Q Enable CE register CLK CLK D Q Enable Power delay down register CLK -75 8.5 7.5 325 130 90 Alliance Semiconductor AS7C251MFT32A AS7C251MFT36A 1M × 32/36 Memory array 32/36 32/ Output Input registers registers CLK 32/36 DQ[a:d] -85 -10 Units 10 12 8.5 10 300 275 130 130 Copyright © ...

Page 2

... PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD- Alliance Semiconductor AS7C251MFT32A AS7C251MFT36A Speed 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/ ...

Page 3

... DQd5 V 26 SSQ V 27 DDQ 28 DQd6 29 DQd7 30 NC/DQPd Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration. DQPn applies to the x36 configuration. 1/17/05, v 1.2 ® TQFP 14 x 20mm Alliance Semiconductor AS7C251MFT32A AS7C251MFT36A 80 DQPb/NC 79 DQb7 78 DQb6 77 V DDQ 76 V SSQ 75 DQb5 74 DQb4 DQb3 ...

Page 4

... WE signals are sampled on the clock edge that samples ADSC low (and ADSP high). • Master chip enable CE0 blocks ADSP, but not ADSC. The AS7C251MFT32A and AS7C251MFT36A family operates from a core 2.5V power supply. These devices are available in 100-pin TQFP package. ...

Page 5

... DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. PUS 1/17/05, v 1.2 ® Description or left floating, device follows interleaved Burst order. When DD is guaranteed after the time t is met. After entering SNOOZE MODE, all inputs except ZZ is SB2 ZZI Alliance Semiconductor AS7C251MFT32A AS7C251MFT36A . The duration of SB2 ...

Page 6

... Address Address Address Address Alliance Semiconductor AS7C251MFT32A AS7C251MFT36A ...

Page 7

... Alliance Semiconductor AS7C251MFT32A AS7C251MFT36A CLK Operation Deselect Deselect Deselect Deselect Deselect External Begin read External Begin read ...

Page 8

... DDQ OUT T stg T bias Symbol Min Nominal V 2.375 2 2.375 2.5 DDQ Vss 0 0 Alliance Semiconductor AS7C251MFT32A AS7C251MFT36A Min Max Unit –0.3 +3.6 –0 0.3 DD –0 0.3 DDQ – 1.8 – –65 +150 –65 +135 Max Unit 2.625 V 2.625 ...

Page 9

... Deselected < Max Deselected < 0.2V, I SB1 ≤ 0.2V or ≥ V all ≥ V Deselected Max I SB2 ≤ ≥ V all Alliance Semiconductor AS7C251MFT32A AS7C251MFT36A Min Max < < OUT DDQ 1.7* V +0.3 DD 1.7* V DDQ -0.3** 0.7 -0.3** 0.7 1.7 – ...

Page 10

... ADSPS t 2.0 – 2.0 ADSCS t 0.5 – 0.5 ADVH t 0.5 – 0.5 ADSPH t 0.5 – 0.5 ADSCH Conditions Symbol ZZ > SB2 t PDS t PUS t ZZI t RZZI Alliance Semiconductor AS7C251MFT32A AS7C251MFT36A –10 Max Min Max Unit Notes – 12 – ns 8.5 – 4.0 – 4.0 ns – 2.5 – ns 2,3,4 – 2.5 – ns – 0 – ns 2,3,4 4.0 – 4.0 ns 2,3,4 5 ...

Page 11

... ADV inserts wait states t HZOE t OH Q(A2Ý01) Q(A2Ý10) Q(A2Ý11 Read Burst Burst Suspend Burst Q(A2) Read Read Read Read Q(A 2Ý01 ) Q(A 2Ý10 ) Q(A 2Ý10 ) Q(A 2Ý11 ) Alliance Semiconductor AS7C251MFT32A AS7C251MFT36A A3 Q(A3) Q(A3Ý01) Q(A3Ý11) Q(A3Ý10) t HZC Read Burst Burst Burst Q(A3) Read Read Read DSEL Q(A 3Ý01 ) Q(A 3Ý10 ) Q(A 3Ý11 ) Undefined ...

Page 12

... CYC t CL ADSC LOADS NEW ADDRESS A2 ADV SUSPENDS BURST D(A2) D(A2Ý01) D(A2Ý01) Read Suspend ADV Suspend Write Q(A2) Write Burst Write D D(A 2Ý01 ) D(A1) Write D(A 2Ý01 ) Alliance Semiconductor AS7C251MFT32A AS7C251MFT36A t ADSCS t ADSCH ADVS t ADVH D(A2Ý10) D(A2Ý11) D(A3) D(A3Ý01) D(A3Ý10) ADV ADV ...

Page 13

... ADVS t ADVH D(A2 HZOE LZOE Q(A3) Suspend Read Suspend Read Read Q(A2) Write Q(A3) Q(A1) D Alliance Semiconductor AS7C251MFT32A AS7C251MFT36A t OH Q(A3Ý01) Q(A3Ý10) Q(A3Ý11) ADV ADV ADV Suspend Burst Burst Burst Read Read Read Read Q(A 3Ý11 ) Q(A 3Ý01 ) Q(A 3Ý10 ) Q(A 3Ý ...

Page 14

... Din READ READ Q(A1) Q(A2) Note: ADV is don’t care here. 1/17/05, v 1.2 ® t CYC HZOE Q(A3) Q(A4 D(A5) D(A6) D(A7) READ WRITE READ WRITE Q(A3) D(A6) Q(A4) D(A5) Alliance Semiconductor AS7C251MFT32A AS7C251MFT36A A10 Q(A9) Q(A10) D(A8) READ WRITE WRITE READ Q(A10) D(A7) D(A8) Q(A9 ...

Page 15

... OE t LZOE Din Dout Q(A1) t PDS ZZ ZZ Setup Cycle t ZZI I supply READ READ Q(A1) Q(A1Ý01) 1/17/05, v 1.2 ® HZC t PUS ZZ Recovery Cycle t RZZI I SB2 Sleep State Alliance Semiconductor AS7C251MFT32A AS7C251MFT36A t CYC HZOE Q(A2) Q(A2(Ý01)) Normal Operation Mode READ READ Q(A2) Q(A2Ý01 ...

Page 16

... DDQ OUT 30 pF* Figure B: Output load (A) at any given temperature and voltage. LZC is measured as low if below VIL. CL Alliance Semiconductor AS7C251MFT32A AS7C251MFT36A Thevenin equivalent: +2.5V 319Ω/1667Ω D OUT /2 5 pF* 353Ω/1538Ω GND *including scope and jig capacitance ...

Page 17

... Package dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 L1 1.00 nominal α 0° 7° Dimensions in millimeters 1/17/05, v 1.2 ® Alliance Semiconductor AS7C251MFT32A AS7C251MFT36A α ...

Page 18

... Ordering information Package & Width AS7C251MFT32A-75TQC TQFP x32 AS7C251MFT32A-75TQI AS7C251MFT36A-75TQC TQFP x36 AS7C251MFT36A-75TQI Note: Add suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C251MFT32A-85TQCN) Part numbering guide AS7C 1.Alliance Semiconductor SRAM prefix 2.Operating voltage 2.5V 3.Organization 4.Flow-through mode 5.Organization ...

Page 19

... Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. AS7C251MFT32A AS7C251MFT36A ® Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C251MFT32A AS7C251MFT36A Document Version: v 1.2 ...

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