BS62LV1027DIP55 BSI [Brilliance Semiconductor], BS62LV1027DIP55 Datasheet

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BS62LV1027DIP55

Manufacturer Part Number
BS62LV1027DIP55
Description
Very Low Power CMOS SRAM 128K X 8 bit
Manufacturer
BSI [Brilliance Semiconductor]
Datasheet
1.BS62LV1027DIP55.pdf (11 pages)
GND
DQ0
DQ1
DQ2
A16
A14
A12
NC
A7
A6
A5
A4
A3
A2
A1
A0
R0201-BS62LV1027
Wide V
Very low power consumption :
High speed access time :
Automatic power down when chip is deselected
Easy expansion with CE2, CE1 and OE options
Three state outputs and TTL compatible
Fully static operation
Data retention supply voltage as low as 1.5V
FEATURES
POWER CONSUMPTION
PIN CONFIGURATIONS
Brilliance Semiconductor, Inc.
V
V
-55
-70
BS62LV1027DC
BS62LV1027PC
BS62LV1027SC
BS62LV1027STC
BS62LV1027TC
BS62LV1027PI
BS62LV1027SI
BS62LV1027STI
BS62LV1027TI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CC
CC
PRODUCT
•
= 3.0V
= 5.0V
BS62LV1027PC
BS62LV1027PI
BS62LV1027SC
BS62LV1027SI
FAMILY
CC
operation voltage : 2.4V ~ 5.5V
VCC
CE2
A13
A15
A16
A14
A12
A11
WE
NC
A9
A8
A7
A6
A5
A4
Operation current : 18mA (Max.) at 55ns
Standby current :
Operation current : 47mA (Max.) at 55ns
Standby current :
55ns (Max.) at V
70ns (Max.) at V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
TEMPERATURE
-40
OPERATING
+0
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
BS62LV1027STC
BS62LV1027STI
BS62LV1027TC
BS62LV1027TI
Commercial
O
Industrial
O
C to +70
C to +85
Pb-Free and Green package materials are compliant to RoHS
CC
CC
Very Low Power CMOS SRAM
128K X 8 bit
: 3.0~5.5V
: 2.7~5.5V
1/1.5uA (Max.) at 70
10mA (Max.) at 1MHz
3/5uA (Max.) at 70
O
O
2mA (Max.) at 1MHz
C
C
V
CC
3.0uA
5.0uA
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
=5.0V V
STANDBY
(I
CCSB1
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
reserves the right to change products and specifications without notice.
, Max.)
O
1.0uA
1.5uA
CC
C/85
O
=3.0V
C/ 85
O
C
O
C
10mA
1MHz
9mA
1
POWER DISSIPATION
The BS62LV1027 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 by 8 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with maximum CMOS standby
current of 1.5/5uA at Vcc=3V/5V at 85
of 55/70ns .
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2), and active LOW output
enable (OE) and three-state output drivers.
The BS62LV1027 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS62LV1027 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 600mil Plastic DIP, 8mmx13.4mm STSOP, and
8mmx20mm TSOP Package
V
10MHz
29mA
30mA
CC
DESCRIPTION
BLOCK DIAGRAM
=5.0V
GND
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A12
A14
A16
A15
A13
CE2
CE1
A11
WE
V
OE
A6
A7
A8
A9
CC
46mA
47mA
f
Max.
Address
Buffer
Operating
Input
(I
Control
CC
, Max.)
8
8
1.5mA
1MHz
2mA
10
Output
Buffer
Buffer
Input
Data
Data
Decoder
Row
V
10MHz
10mA
CC
9mA
=3.0V
8
BS62LV1027
O
8
C and maximum access time
1024
17mA
18mA
f
A5
Max.
A10
Address Input Buffer
Column Decoder
Memory Array
1024 x 1024
Write Driver
Column I/O
Sense Amp
A4 A3 A2 A1 A0
Revision
Oct.
DICE
PDIP-32
SOP-32
STSOP-32
TSOP-32
PDIP-32
SOP-32
STSOP-32
TSOP-32
PKG TYPE
1024
128
7
2008
2.4

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BS62LV1027DIP55 Summary of contents

Page 1

Very Low Power CMOS SRAM 128K X 8 bit Pb-Free and Green package materials are compliant to RoHS FEATURES Wide V operation voltage : 2.4V ~ 5.5V CC Very low power consumption : V = 3.0V Operation current : 18mA ...

Page 2

PIN DESCRIPTIONS Name A0-A16 Address Input CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input WE Write Enable Input OE Output Enable Input DQ0-DQ7 Data Input/Output Ports V CC GND TRUTH TABLE CE1 MODE H Not selected (Power Down) ...

Page 3

DC ELECTRICAL CHARACTERISTICS (T PARAMETER PARAMETER NAME V Power Supply CC V Input Low Voltage IL V Input High Voltage IH I Input Leakage Current IL I Output Leakage Current LO V Output Low Voltage OL V Output High Voltage ...

Page 4

LOW V DATA RETENTION WAVEFORM (2) (CE2 Controlled CE2 AC TEST CONDITIONS (Test Load and Input/Output Reference) Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level ...

Page 5

SWITCHING WAVEFORMS (READ CYCLE) (1,2,4) READ CYCLE 1 ADDRESS D OUT (1,3,4) READ CYCLE 2 CE1 CE2 D OUT (1, 4) READ CYCLE 3 ADDRESS OE CE1 CE2 D OUT NOTES high in read Cycle. 2. Device ...

Page 6

AC ELECTRICAL CHARACTERISTICS (T WRITE CYCLE JEDEC PARAMETER PARAMETER NAME NAME t t AVAX E1LWH AVWL AVWH WLWH WHAX WR1 t t E2LAX WR2 t ...

Page 7

WRITE CYCLE 2 ADDRESS CE1 CE2 WE D OUT D IN NOTES must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and ...

Page 8

ORDERING INFORMATION BS62LV1027 Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the ...

Page 9

PACKAGE DIMENSIONS (continued) STSOP - 32 TSOP - 32 R0201-BS62LV1027 9 BS62LV1027 Revision 2.4 Oct. 2008 ...

Page 10

PACKAGE DIMENSIONS (continued) PDIP - 32 R0201-BS62LV1027 10 BS62LV1027 Revision 2.4 Oct. 2008 ...

Page 11

Revision History Revision No. History 2.2 Add Icc1 characteristic parameter Improve Iccsb1 spec. I-grade from 20uA to 5.0uA at 5.0V C-grade from 8.0uA to 3.0uA at 5.0V 2.3 Change I-grade operation temperature range - from –25 O 2.4 Typical value ...

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