AS7C252MNTD18A-133TQC ALSC [Alliance Semiconductor Corporation], AS7C252MNTD18A-133TQC Datasheet
AS7C252MNTD18A-133TQC
Related parts for AS7C252MNTD18A-133TQC
AS7C252MNTD18A-133TQC Summary of contents
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... CLK Control logic CLK 18 18 Data D Q Input Register CLK OE -200 -166 5 200 166 3.2 3.5 450 400 170 150 90 90 Alliance Semiconductor AS7C252MNTD18A CLK SRAM Array CLK Output Register OE 18 DQ[a,b] -133 Units 6 7.5 ns 133 MHz 3.8 ns 350 mA ...
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... Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD- Alliance Semiconductor AS7C252MNTD18A Speed 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/ ...
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... V 20 DDQ V 21 SSQ DQb6 22 DQb7 23 24 DQPb SSQ V 27 DDQ 1/17/05, V 1.2 ® TQFP 14 x 20mm Alliance Semiconductor AS7C252MNTD18A DDQ 76 V SSQ DQPa DQa7 73 72 DQa6 V 71 SSQ 70 V DDQ 69 DQa5 68 DQa4 ...
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... Functional description The AS7C252MNTD18A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory (SRAM) organized as 2,097,152 words × 18 bits and incorporates a LATE LATE Write. This variation of the 32Mb+ synchronous SRAM uses the No Turnaround Delay (NTD operation that improves bandwidth over pipelined burst devices normal pipelined burst device, the write data, command, and address are all applied to the device on the same clock edge ...
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... DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE PUS MODE. 1/17/05, V 1.2 ® or left floating, device follows interleaved Burst order. When DD is guaranteed after the time t is met. After entering SNOOZE MODE, all inputs except ZZ SB2 ZZI Alliance Semiconductor AS7C252MNTD18A . The duration of SB2 ...
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... X L External NOP/WRITE ABORT (Begin Burst) High Next Current and BW b enables WRITEs to byte “b” (DQb pins). Alliance Semiconductor AS7C252MNTD18A ...
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... Write Symbol DDQ OUT T stg T bias Symbol Min V 2.375 DD V 2.375 DDQ Vss 0 Alliance Semiconductor AS7C252MNTD18A Burst Dsel Burst Burst Min Max Unit –0.3 +3.6 –0 0.3 DD –0 0.3 DDQ – 1.8 – –65 +150 –65 +135 Nominal Max 2 ...
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... V All V – 0.2V, Deselected < Max IL Deselected < 0.2V, ≤ 0.2V or ≥ V all V – 0. ≥ V Deselected Max DD ≤ ≥ V all Alliance Semiconductor AS7C252MNTD18A Min Max -2 < OUT DDQ * 1 1.7 V DDQ ** -0.3 0.7 ** -0.3 0.7 1.7 – 0.7 -200 -166 ...
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... CSH t 1.4 – 1.5 CENS t 0.4 – 0.5 CENH t 1.4 – 1.5 ADVS t 0.4 – 0.5 ADVH Conditions Symbol ZZ > SB2 t PDS t PUS t ZZI t RZZI Alliance Semiconductor AS7C252MNTD18A -133 1 Unit Notes Max Min Max 166 – 133 MHz – 7.5 – ns 3.5 – 3.8 ns 3.5 – 3.8 ns – 0 – ns 2,3,4 – 1.5 – – 0 – ...
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... Falling input HZOE OE Q(A1) Q(A2) Q(A2Y‘01) Read Continue Continue Continue Q(A2) Read Read Q(A2Y‘10) Q(A2Y‘01) Q(A2Y‘11) Alliance Semiconductor AS7C252MNTD18A Undefined t CYC A3 Q(A2Y‘10) Q(A3) Q(A2Y‘11) Continue Inhibit Read Read Read Clock Q(A3) Q(A3Y‘01 HLZC ...
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... HZOE Dout Q(n-2) Q(n-1) Write DSEL D(A1) 1/17/05, V 1.2 ® D(A1) D(A2) D(A2Y‘01) Write Continue Continue Continue D(A2) Write Write Write D(A2Y‘10) D(A2Y‘01) D(A2Y‘11) Alliance Semiconductor AS7C252MNTD18A t CYC D(A3) D(A2Y‘10) D(A2Y‘11) Continue Inhibit Write Write Clock D(A3) D(A3Y‘01 ...
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... Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low. BW[a:d] is don’t care. 1/17/05, V 1.2 ® LZC OH D(A1) D(A2) Q(A3) D(A2Ý01) Burst Burst Read Read Write Read Q(A3) Q(A4) D(A2Ý01) Q(A4Ý01) Alliance Semiconductor AS7C252MNTD18A t CYC HZC D(A5) Q(A6) Q(A4) Q(A4Ý01) t HZOE t LZOE Write Read Write D(A5) Q(A6) D(A7 DSEL ...
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... Address A1 D/Q Command Read Burst Q(A1) Q(A1Ý01) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low low. 1/17/05, V 1.2 ® A2 Q(A1Ý01) Q(A1) Q(A1Ý10) STALL Burst DSEL Burst Q(A1Ý10) DSEL Alliance Semiconductor AS7C252MNTD18A A3 D(A2) Burst Write Write Burst NOP NOP D(A2) D(A2Ý10) D(A2Ý01) D(A3 ...
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... Timing waveform of snooze mode CLK ZZ setup cycle ZZ t ZZI I supply I SB2 All inputs Deselect or Read Only (except ZZ) Dout 1/17/05, V 1.2 ® t PUS ZZ recovery cycle t RZZI Deselect or Read Only High-Z Alliance Semiconductor AS7C252MNTD18A Normal operation Cycle ...
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... Figure C. For all others, see Figure B. HZC 50Ω DDQ 30 pF* Figure B: Output load (A) at any given temperature and voltage. LZC IL Alliance Semiconductor AS7C252MNTD18A Thevenin equivalent: +2.5V 319Ω/1667Ω D 7Ω /2 OUT 5 pF* 353Ω/1538Ω GND *including scope and jig capacitance Figure C: Output load(B) P ...
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... Package dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.90 16.10 He 21.90 22.10 L 0.45 0.75 L1 1.00 nominal α 0° 7° Dimensions in millimeters 1/17/05, V 1.2 ® Alliance Semiconductor AS7C252MNTD18A b e α ...
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... Clock speed (MHz) 8. Package type TQFP 9. Operating temperature commercial ( 0° 70° C industrial ( -40 ° 85° Lead Free Part 1/17/05, V 1.2 ® –166 MHz AS7C252MNTD18A-166TQC AS7C252MNTD18A-166TQI AS7C252MNTD18A-200TQCN) NTD 18 A –XXX Alliance Semiconductor AS7C252MNTD18A –133 MHz AS7C252MNTD18A-133TQC AS7C252MNTD18A-133TQI TQ C ...
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... Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. AS7C252MNTD18A ® Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C252MNTD18A Document Version: V 1.2 ...