SH3000EK SEMTECH [Semtech Corporation], SH3000EK Datasheet - Page 11

• Manufacturer Part Number: SH3000EK
• Description: Reset Management and Clock Management Support IC for Microcontrollers
• Manufacturer: SEMTECH [Semtech Corporation]

Interrupt and Serial Interface
information between the SH3002 and the processor, and
as the interrupt line to the processor.
communicate using a single wire, bi-directional
asynchronous serial interface. The bit rate is
automatically determined by the SH3002. . At the
fastest possible rate, a read or write access of a single
byte from the register bank takes 5 µs.
located at 0x00–0x1F. Some of these registers are
accessed through a page operation. Pin 14, IO/Int, is
the serial communications interface and interrupt output
pin. This pin is internally weakly pulled to the opposite of
the programmed interrupt polarity. For example, if
interrupt is programmed to be active low, this pin is
weakly pulled to V
communicate with serial data streams. The host always
initiates communication. A data stream consists of the
following (in this order):
interrupt polarity) uses the middle bit to determine the bit
period of the serial data stream.
read, or 0,1,1 for a write. This protects against early
glitches that might otherwise put the interface into an
invalid read or write access mode.
register.
which to change data direction. The value of a guard bit
does not matter.
register.
Copyright ©2002-2005 Semtech Corporation
SYSTEM MANAGEMENT
A single line is used to convey bi-directional
The polarity of the interrupt signal is programmable.
The SH3002 and the host microcontroller
The SH3002 contains 36 addressable registers
As shown in Figure 7, the SH3002 and the host
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•
•
•
•
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Plus, for write streams only:
•
•
The 3-bit start field (1,0,1 or 0,1,0, depending on
The 3-bit read/write code consists of 1,1,0 for a
The 5-bit address field contains the address of the
A single guard bit gives the interface a safe period in
The 8-bit data field is written to (read from) the
3-bit start field
3-bit read/write code
5-bit address field
1 guard bit
8-bit data field
2 parity bits
1 guard bit
2 acknowledge (ACK) bits
DD
when inactive.
11
Table 3: Minimum/Maximum Serial Bit Timing
Frequency
CLK
16 MHz
8 MHz
2 MHz
are an odd number of bits in the read/write, address and
data fields; the second parity bit is the inverse of the first.
the stream (to allow safe turnaround), and then two
acknowledge bits, which are a direct copy of the parity
bits, are driven back to the host to indicate a successful
write access.
access stream (read or write). The host can not start the
next access before receiving these bits.
the start bit field, and communication can take place
whenever CLK
higher frequency. If the host microcontroller is running
synchronously to the CLK
(which should generally be the case), then a minimum of
4 CLK
communication integrity. If the host’s serial interface is
asynchronous to CLK
per bit are necessary. A maximum of 1024 CLK
cycles per bit field is supported.
periods for the serial communications for CLK
frequencies of 16 MHz, 8 MHz, and 2 MHz.
Interrupt Interface
14, IO/Int) also serves as the interrupt to the host
microcontroller. The polarity of the interrupt is software
programmable using the interrupt polarity bit (bit 6) of the
IPol_RCtune register (R0x11). This pin is asserted for
four cycles of CLK
state.
Interrupt/Wake-up Timer to interrupt the host when it
reaches its end of count.
OUT
Two parity bits: The first parity bit is high when there
For write streams only, a guard bit is appended to
Two guard bits are appended to the end of the
The interface is self-timed based on the duration of
Table 3 displays the minimum and maximum bit
The serial communications line to the SH3002 (Pin
The interrupt line is used by the Periodic
OUT
cycles per bit are required to maintain
synchronous
to
Minimum Bit
CLK
OUT
Period
250 ns
500 ns
(host
2 µs
OUT
is active, either at 32.768 kHz or at a
OUT
OUT
, and then returns to the inactive
SH3002 MicroBuddy™
)
, then a minimum of 52 cycles
OUT
asynchronous
Minimum Bit
to
V1.20
generated by the SH3002
CLK
3.25 µs
Period
6.5 µs
(host
26 µs
OUT
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)
OUT
Maximum Bit
OUT
63.9 µs
Period
127 µs
511 µs