EVAL-CONTROLBRD AD [Analog Devices], EVAL-CONTROLBRD Datasheet - Page 17

• Manufacturer Part Number: EVAL-CONTROLBRD
• Description: 16-Bit, 1.33 MSPS PulSAR ADC in MSOP/QFN
• Manufacturer: AD [Analog Devices]

CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7983 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 26, and the corresponding timing is given in
Figure 27.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. When a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for example, to bring CNV low to select other SPI devices, such
as analog multiplexers; however, CNV must be returned high
before the minimum conversion time elapses and then held
high for the maximum conversion time to avoid the generation
of the busy signal indicator. When the conversion is complete, the
AD7983 enters the acquisition phase and goes into standby mode.
ACQUISITION
SDI = 1
CNV
SCK
SDO
Figure 27. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
CONVERSION
t
CONV
t
CNVH
t
EN
D15
1
Rev. 0 | Page 17 of 24
t
HSDO
D14
t
2
CYC
ACQUISITION
D13
When CNV goes low, the MSB is output onto SDO. The
remaining data bits are then clocked by subsequent SCK falling
edges. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate provided that it has an
acceptable hold time. After the 16th SCK falling edge or when
CNV goes high, whichever is earlier, SDO returns to high
impedance.
t
3
ACQ
t
DSDO
t
SCKL
VIO
14
t
SCKH
Figure 26. CS Mode, 3-Wire Without Busy Indicator
SDI
t
SCK
AD7983
15
Connection Diagram (SDI High)
D1
CNV
SCK
16
D0
SDO
t
DIS
CONVERT
DATA IN
CLK
DIGITAL HOST
AD7983