24LC512 Microchip Technology Inc., 24LC512 Datasheet

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24LC512

Manufacturer Part Number
24LC512
Description
SOP8
Manufacturer
Microchip Technology Inc.
Datasheets

Specifications of 24LC512

Date_code
09+

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Device Selection Table
Features
• Low power CMOS technology
• 2-wire serial interface bus, I
• Cascadable for up to eight devices
• Self-timed ERASE/WRITE cycle
• 128-byte Page-Write mode available
• 5 ms max write-cycle time
• Hardware write-protect for entire array
• Schmitt Trigger inputs for noise suppression
• 1,000,000 erase/write cycles
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP, SOIC(208 mil), and DFN packages
• 14-lead TSSOP package
• Temperature ranges:
Package Type
*24XX512 is used in this document as a generic part number for the 24AA512/24LC512/24FC512 devices.
 2002 Microchip Technology Inc.
Note 1: 100 kHz for V
24AA512
24LC512
24FC512
- Maximum write current 3 mA at 5.5V
- Maximum read current 400 µA at 5.5V
- Standby current 100 nA typical at 5.5V
- Industrial (I):
- Automotive (E):
Number
V
A0
A1
A2
SS
Part
1
2
3
4
PDIP
1.8-5.5V
2.5-5.5V
2.5-5.5V
Range
V
CC
8
7
6
5
512K I
CC
-40°C to +85°C
-40°C to +125°C
V
WP
SCL
SDA
CC
< 2.5V.
Max. Clock
Frequency
400 kHz
2
400 kHz
C compatible
1 MHz
V
A0
A1
A2
SS
2
(1)
24AA512/24LC512/24FC512
C
1
2
3
4
Ranges
SOIC
Temp.
I, E
CMOS Serial EEPROM
I
I
8
7
6
5
V
WP
SCL
SDA
CC
Description
The Microchip Technology Inc. 24AA512/24LC512/
24FC512 (24XX512*) is a 64K x 8 (512 Kbit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.8V to 5.5V). It has
been developed for advanced, low power applications
such as personal communications and data acquisi-
tion. This device also has a page-write capability of up
to 128 bytes of data. This device is capable of both ran-
dom and sequential reads up to the 512K boundary.
Functional address lines allow up to eight devices on
the same bus, for up to 4 Mbit address space. This
device is available in the standard 8-pin plastic DIP,
SOIC, DFN and 14-lead TSSOP packages.
Block Diagram
V
SDA
NC
NC
NC
CONTROL
I/O
A0
A1
A2
SS
LOGIC
I/O
V
V
CC
SS
1
2
3
4
5
6
7
SCL
TSSOP
A0 A1 A2
CONTROL
MEMORY
14
13
12
10
11
LOGIC
9
8
WP
V
WP
NC
NC
NC
SCL
SDA
CC
XDEC
V
A0
A1
A2
SS
1
2
3
4
DS21754A-page 1
HV GENERATOR
DFN
PAGE LATCHES
R/W CONTROL
SENSE AMP
EEPROM
ARRAY
YDEC
8
7
6
5
V
WP
SCL
SDA
CC

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