TS80C32X2MCB TEMIC Semiconductors, TS80C32X2MCB Datasheet

TS80C32X2MCB

Manufacturer Part Number

TS80C32X2MCB

Description

PLCC

Manufacturer

TEMIC Semiconductors

Datasheet

1.TS80C32X2MCB.pdf (56 pages)

Specifications of TS80C32X2MCB

Date_code

08+

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8-bit CMOS Microcontroller 0-60 MHz

1. Description

TEMIC TS80C52X2 is high performance CMOS ROM,

OTP, EPROM and ROMless versions of the 80C51

CMOS single chip 8-bit microcontroller.

The TS80C52X2 retains all features of the TEMIC

80C51 with extended ROM/EPROM capacity (8

Kbytes), 256 bytes of internal RAM, a 6-source , 4-level

interrupt system, an on-chip oscilator and three timer/

counters.

In addition, the TS80C52X2 has a dual data pointer, a

multiprocessor communication (EUART) and a X2 speed

improvement mechanism.

2. Features

Rev. C - Aug. 31, 1999

80C52 Compatible

High-Speed Architecture

Dual Data Pointer

On-chip ROM/EPROM (8K-bytes)

Programmable Clock Out and Up/Down Timer/

Counter 2

Asynchronous port reset

8051 pin and instruction compatible

Four 8-bit I/O ports

Three 16-bit timer/counters

256 bytes scratchpad RAM

40 MHz @ 5V, 30MHz @ 3V

X2 Speed Improvement capability (6 clocks/

machine cycle)

30 MHz @ 5V, 20 MHz @ 3V (Equivalent to

60 MHz @ 5V, 40 MHz @ 3V)

versatile

serial

channel

that

Preliminary

facilitates

The fully static design of the TS80C52X2 allows to

reduce system power consumption by bringing the clock

frequency down to any value, even DC, without loss of

data.

The TS80C52X2 has 2 software-selectable modes of

reduced activity for further reduction in power

consumption. In the idle mode the CPU is frozen while

the timers, the serial port and the interrupt system are still

operating. In the power-down mode the RAM is saved

and all other functions are inoperative.

Interrupt Structure with

Full duplex Enhanced UART

Low EMI (inhibit ALE)

Power Control modes

Once mode (On-chip Emulation)

Power supply: 4.5-5V, 2.7-5.5V

Temperature ranges: Commercial (0 to 70

Industrial (-40 to 85

Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1

(13.9

(window)

6 Interrupt sources,

4 level priority interrupt system

Framing error detection

Automatic address recognition

Idle mode

Power-down mode

Power-off Flag

footprint),

CQPJ44

(window),

TS80C32X2

TS87C52X2

TS80C52X2

CDIL40

C) and

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