XRD9816BCV Exar Corporation, XRD9816BCV Datasheet

XRD9816BCV

Manufacturer Part Number

XRD9816BCV

Description

QFP

Manufacturer

Exar Corporation

Datasheets

1.XRD9816BCV.pdf (53 pages)

2.XRD9816BCV.pdf (53 pages)

Specifications of XRD9816BCV

Date_code

04+

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FEATURES

GENERAL DESCRIPTION

The XRD9814B/9816B is a fully integrated, high-per-

formance analog signal processor/digitizer specifi-

cally designed for use in 3-channel linear Charge

Coupled Device (CCD) and Contact Image Sensitive

(CIS) imaging applications.

Each channel of the XRD9814B/9816B includes a

Correlated Double Sampler (CDS), Programmable

Gain Amplifier (PGA) and channel offset adjustment.

After gain and offset adjustment, the analog inputs are

sequentially sampled and digitized by an accurate 14/

16-bit A/D converter. The analog front-end can be

configured for inverting/non-inverting input, CDS or

sample-hold (S/H)

making the XRD9814B/9816B suitable for use in CCD,

CIS and other data acquisition applications.

ORDERING INFORMATION

EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017

14-Bit (XRD9814B) or 16-Bit (XRD9816B)

A/D Converter

Triple-Channel, 2.5 MSPS Color Scan Mode

Single-Channel, 6 MSPS Monochrome Scan

Mode

Triple Correlated Double Sampler

Triple 10-Bit Programmable Gain Amplifier

Triple 10-Bit Offset Compensation DAC

Fully Differential or Single-Ended Inputs

CDS or S/H Mode

Inverting or Non-Inverting Mode

Internal Voltage Reference

Serial Control: On Data Bus or Separate Pins

Improved PGA Performance

Rev. 1.00

mode,

XRD9814BCV

XRD9816BCV

Part No.

AC/DC

coupling,

Package Type

48-Lead TQFP

XRD9814B/XRD9816B

APPLICATIONS

The CDS mode of operation supports both line and

pixel-clamp modes and can be used to achieve signifi-

cant reduction in system 1/f noise and CCD reset

clock feed-through. In S/H mode the internal DC-

restore voltage clamp can be enabled or disabled to

support AC-coupled or DC inputs. Sampling mode,

10-bit PGA gain (1024 linear steps), 8-bit fine offset

adjustment (256 linear steps), 2-bit gross offset adjust-

ment and input signal polarity are all programmable

through a serial interface. PGA gain range is 1 to 10,

and channel offset range is -300mV to 300mV for fine

adjustment and additional -400mV to +200mV for

gross offset adjustment. The A/D Full-Scale Range

(FSR) is programmable to 2V or 3V.

CCD/CIS Sensor Signal Processors

14-Bit or 8-Bit (Nibble) Parallel Data Output

(XRD9814B)

16-Bit or 8-Bit (Nibble) Parallel Data Output

(XRD9816B)

5V Operation and 3V I/O Compatibility

Low Power CMOS: 500mW @ 5V

48-Bit Color Scanners (XRD9816B)

42-Bit Color Scanners (XRD9814B)

CCD or CIS Color Imagers

Gray Scale Scanners

Film Scanners

Temperature Range

3-Channel 14/16-Bit Linear

0°C to +70°C

www.exar.com

November 2002-2

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