MC10EP131FA ON Semiconductor, MC10EP131FA Datasheet

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MC10EP131FA

Manufacturer Part Number
MC10EP131FA
Description
Manufacturer
ON Semiconductor
Datasheet

Specifications of MC10EP131FA

Case
QFP
Date_code
07

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MC10EP131, MC100EP131
3.3V / 5V ECL Quad D
Flip−Flop with Set, Reset,
and Differential Clock
Description
common set and separate resets. The device is an expansion of the
E131 with differential common clock and individual clock enables.
With AC performance faster than the E131 device, the EP131 is ideal
for applications requiring the fastest AC performance available.
Clock (C
Enable inputs for clocking (C
C
Clock (C
differential input will disable operation due to input pulldown resistors
forcing an output default state.
(SET) are provided.
transfers to the slave when either C
Features
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 10
0−3
The MC10/100EP131 is a Quad Master−slaved D flip−flop with
Each flip−flop may be clocked separately by holding Common
Common clocking is achieved by holding the differential inputs
Individual asynchronous resets (R
Data enters the master when both C
The 100 Series contains temperature compensation.
with V
with V
460 ps Typical Propagation Delay
Maximum Frequency > 3 GHz Typical
Differential Individual and Common Clocks
Individual Asynchronous Resets
Asynchronous Set
PECL Mode Operating Range: V
NECL Mode Operating Range: V
Open Input Default State
Safety Clamp on Inputs
Q Output Will Default LOW with Inputs Open or at V
Pb−Free Packages are Available
LOW and C
C
C
EE
EE
) to clock all four flip−flops. When left floating open, any
) LOW and C
= −3.0 V to −5.5 V
= 0 V
0−3
HIGH while using the differential Common
C
HIGH, then using the differential Clock
0−3
, C
C
0−3
CC
CC
or C
0−3
).
= 3.0 V to 5.5 V
= 0 V
) and an asynchronous set
C
0−3
and C
(or both) go HIGH.
0−3
are LOW, and
EE
1
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
*For additional marking information, refer to
(Note: Microdot may be in either location)
Application Note AND8002/D.
CASE 488AM
CASE 873A
FA SUFFIX
MN SUFFIX
LQFP−32
QFN32
ORDERING INFORMATION
xxx
A
WL, L
YY, Y
WW, W = Work Week
G or G
1
http://onsemi.com
32
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Pb−Free Package
Publication Order Number:
1
AWLYYWWG
AWLYYWWG
DIAGRAM*
MARKING
MCxxx
EP131
MCxxx
EP131
MC10EP131/D
G

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