MC74HC573ADTG ON Semiconductor, MC74HC573ADTG Datasheet - Page 5

• Manufacturer Part Number: MC74HC573ADTG
• Description: IC LATCH TRANSP OCTAL 20-TSSOP
• Manufacturer: ON Semiconductor
• Series: 74HCr
• Type: D-Typer

Specifications of MC74HC573ADTG

• Logic Type: D-Type Transparent Latch
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 2 V ~ 6 V
• Independent Circuits: 1
• Delay Time - Propagation: 26ns
• Current - Output High, Low: 7.8mA, 7.8mA
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Number Of Circuits: 8
• Logic Family: 74HC
• Polarity: Non-Inverting
• Input Bias Current (max): 4 uA
• High Level Output Current: - 7.8 mA
• Low Level Output Current: 32 mA
• Propagation Delay Time: 150 ns at 2 V, 100 ns at 3 V, 30 ns at 4.5 V, 26 ns at 6 V
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Mounting Style: SMD/SMT
• Number Of Bits: 8
• Number Of Elements: 1
• Latch Mode: Transparent
• Technology: CMOS
• Package Type: TSSOP
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 6V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DEVICE
UNDER
TEST
OUTPUT
ENABLE
INPUT D
Q
Q
Q
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
t
PLH
t
r
OUTPUT
t
DEVICE
TLH
UNDER
50%
TEST
Figure 5. Test Circuit
Figure 6. Test Circuit
MC74HC573A: V
MC74HCT573A: V
TEST POINT
10%
10%
V
50%
50%
V
90%
90%
M
M
Figure 1.
Figure 3.
t
t
PZL
PZH
C
1 kW
L
OUTPUT
*
t
t
PHZ
M
PLZ
M
= V
TEST POINT
= 1.3 V @ V
OH
CONNECT TO V
TESTING t
CONNECT TO GND WHEN
TESTING t
x 0.5
C
t
f
L
*
CC
SWITCHING WAVEFORMS
10%
90%
PLZ
PHZ
t
= 3 V
PHL
t
THL
AND t
AND t
http://onsemi.com
CC
V
GND
V
GND
HIGH
IMPEDANCE
V
V
HIGH
IMPEDANCE
CC
WHEN
CC
OL
OH
PZL
PZH
.
.
5
ENABLE
OUTPUT ENABLE
LATCH
INPUT D
LATCH ENABLE
ENABLE
LATCH
D0
D1
D2
D3
D4
D5
D6
D7
Q
Figure 7. EXPANDED LOGIC DIAGRAM
2
3
4
5
6
7
8
9
50%
50%
11
1
50%
t
w
t
PLH
t
SU
Figure 2.
Figure 4.
VALID
50%
t
PHL
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
t
h
Q
Q
Q
Q
Q
Q
Q
Q
19
18
17
16
15
14
13
12
V
GND
V
GND
V
GND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CC
CC
CC