MC14043B, MC14044B
CMOS MSI
Quad R−S Latches
with MOS P−Channel and N−Channel enhancement mode devices in a
single monolithic structure. Each latch has an independent Q output
and set and reset inputs. The Q outputs are gated through three−state
buffers having a common enable input. The outputs are enabled with a
logical “1” or high on the enable input; a logical “0” or low
disconnects the latch from the Q outputs, resulting in an open circuit at
the Q outputs.
Features
•
•
•
•
•
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
(e.g., either V
*For additional information on our Pb−Free strategy and soldering details, please
MAXIMUM RATINGS
© Semiconductor Components Industries, LLC, 2005
Symbol
V
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
I
The MC14043B and MC14044B quad R−S latches are constructed
in
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level
Low−Power Schottky TTL Load Over the Rated Temperature Range
in
Double Diode Input Protection
Three−State Outputs with Common Enable
Outputs Capable of Driving Two Low−power TTL Loads or One
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Pb−Free Packages are Available*
V
T
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
P
, V
, I
T
T
stg
DD
A
D
L
out
out
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation, per Package
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
SS
(DC or Transient)
(DC or Transient) per Pin
(Note 1)
(8−Second Soldering)
or V
v (V
DD
in
). Unused outputs must be left open.
Parameter
or V
(Voltages Referenced to V
out
) v V
DD
.
in
and V
−0.5 to V
SS
−0.5 to +18.0
−55 to +125
−65 to +150
out
)
Value
± 10
500
260
should be constrained
DD
+ 0.5
1
Unit
mW
mA
°C
°C
°C
V
V
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
xx
A
WL, L
YY, Y
WW, W
G
CASE 751B
SOEIAJ−16
CASE 648
CASE 966
P SUFFIX
D SUFFIX
F SUFFIX
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
PDIP−16
SOIC−16
Publication Order Number:
16
1
16
16
1
1
DIAGRAMS
MARKING
MC140xxBCP
AWLYYWWG
MC140xxB
AWLYWW
MC14043B/D
140xxBG
ALYWG