CY7C254-65WC Cypress Semiconductor Corporation., CY7C254-65WC Datasheet
CY7C254-65WC
Manufacturer Part Number
CY7C254-65WC
Description
Manufacturer
Cypress Semiconductor Corporation.
Specifications of CY7C254-65WC
Date_code
00+
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
CY7C254-65WC
Manufacturer:
CYP
Quantity:
900
Company:
Part Number:
CY7C254-65WC
Manufacturer:
CYPRESS
Quantity:
900
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Part Number:
CY7C254-65WC
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Quantity:
295
Features
Cypress Semiconductor Corporation
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
• Low power
• Super low standby power (7C251)
• EPROM technology 100% programmable
• Slim 300-mil or standard 600-mil packaging available
• 5V 10% V
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
• Capable of withstanding >2001V static discharge
— 45 ns
— 550 mW (commercial)
— 660 mW (military)
— Less than 165 mW when deselected
— Fast access: 50 ns
A
A
A
A
CS
CS
CS
CS
Logic Block Diagram
A
A
A
A
A
A
A
A
A
A
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
2
3
4
DECODER
ADDRESS
ADDRESS
ADDRESS
COLUMN
CC
ROW
, commercial and military
X
Y
PROGRAMABLE
512 x 256
ARRAY
POWER-DOWN
(7C251)
MULTIPLEXER
8 x 1 OF 32
•
3901 North First Street
Functional Description
The
16,384-word by 8-bit CMOS PROMs. When deselected, the
CY7C251 automatically powers down into a low-power
stand-by mode. It is packaged in a 300-mil-wide package. The
7C254 is packaged in a 600-mil-wide package and does not
power down when deselected. The 7C251 and 7C254 are
available in reprogrammable packages equipped with an era-
sure window; when exposed to UV light, these PROMs are
erased and can then be reprogrammed. The memory cells uti-
lize proven EPROM floating gate technology and byte-wide
intelligent programming algorithms.
The CY7C251 and CY7C254 are plug-in replacements for bi-
polar devices and offer the advantages of lower power, supe-
rior performance, and high programming yield. The EPROM
cell requires only 12.5V for the super voltage, and low current
requirements allow for gang programming. The EPROM cells
allow each memory location to be tested 100% because each
location is written into, erased, and repeatedly exercised prior
to encapsulation. Each PROM is also tested for AC perfor-
mance to guarantee that after customer programming, the
product will meet DC and AC specification limits.
Reading is accomplished by placing all four chip selects in
their active states. The contents of the memory location ad-
dressed by the address lines (A
the output lines (O
16K x 8 Power Switched and
C251-1
CY7C251
O
O
O
O
O
O
O
O
•
7
6
5
4
3
2
1
0
Pin Configurations
San Jose
Reprogrammable PROM
0
November 1986 – Revised December 1992
– O
and
7
).
•
CY7C254
CA 95134
A
A
A
A
NC
O
O
A
A
GND
5
4
3
2
1
0
0
1
0
O
O
O
A
A
A
A
A
A
A
A
A
A
– A
9
8
7
6
5
4
3
2
1
0
0
1
2
5
6
7
8
9
10
11
12
13
14151617
DIP/Flatpack
13
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
are
3 2 1
) will become available on
7C254
7C251
7C254
7C251
LCC
32
181920
•
high-performance
28
27
26
25
24
23
22
21
20
19
18
17
16
15
31
CY7C251
CY7C254
30
408-943-2600
29
28
27
26
25
24
23
22
21
CS
CS
CS
CS
V
A
A
A
A
O
O
O
O
O
CC
10
11
12
13
7
6
5
4
3
1
2
3
4
CS
CS
CS
CS
A
NC
O
O
C251-2
A
13
12
7
6
C251-3
1
2
3
4
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