74F675ASC Fairchild Semiconductor, 74F675ASC Datasheet
74F675ASC
Specifications of 74F675ASC
Related parts for 74F675ASC
74F675ASC Summary of contents
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... A HIGH signal on the Chip Select input prevents both shifting and parallel loading. Ordering Code: Order Number Package Number 74F675ASC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F675APC N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide ...
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Unit Loading/Fan Out Pin Names SI Serial Data Input Chip Select Input (Active LOW) CS Shift Clock Pulse Input (Active Falling Edge) SHCP STCP Store Clock Pulse Input (Active Rising Edge) Read/Write Input R/W SO Serial Data Output Q –Q ...
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Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2) Input Current (Note 5.0 mA Voltage Applied to Output in HIGH State ...
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AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PLH t STCP to Q PHL n t Propagation Delay PLH t SHCP to SO PHL AC Operating Requirements Symbol Parameter t (H) Setup Time, HIGH or ...
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Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide Package Number M24B Package Number N24A 5 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...