74F322PC Fairchild Semiconductor, 74F322PC Datasheet - Page 2

• Manufacturer Part Number: 74F322PC
• Description: IC REGISTER SER/PAR W/EXT 20-DIP
• Manufacturer: Fairchild Semiconductor
• Series: 74Fr

Specifications of 74F322PC

• Logic Type: Register, Multiplexed
• Output Type: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Function: Serial to Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74F322

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Unit Loading/Fan Out
Functional Description
The 74F322 contains eight D-type edge triggered flip-flops
and the interstage gating required to perform right shift and
the intrastage gating necessary for hold and synchronous
parallel load operations. A LOW signal on RE enables shift-
ing or parallel loading, while a HIGH signal enables the
hold mode. A HIGH signal on S/P enables shift right, while
a LOW signal disables the 3-STATE output buffers and
enables parallel loading. In the shift right mode a HIGH sig-
Mode Select Table
H
L

Z
NC
Note: I
from the I/O terminal.
Note: D
Note: O
Note 1: When the OE input is HIGH all I/O
LOW Voltage Level
High Impedance Output State
HIGH Voltage Level
Clear
Parallel
Load
Shift
Right
Sign
Extend
Hold
LOW-to-HIGH Transition
RE
S/P
SE
S
D
CP
MR
OE
Q
I/O
No Change
Pin Names
Mode
7
0
0
–I
0
7
, D
, D
–O
0
0
–I/O
1
0
1
The level of the steady-state input at the respective I/O terminal is loaded into the flip-flop while the flip-flop outputs (except Q
The level of the steady-state inputs to the serial multiplexer input.
The level of the respective Q
7
MR
H
H
H
H
H
L
L
Register Enable Input (Active LOW)
Serial (HIGH) or Parallel (LOW) Mode Control Input
Sign Extend Input (Active LOW)
Serial Data Select Input
Serial Data Inputs
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
3-STATE Output Enable Input (Active LOW)
Bi-State Serial Output
Multiplexed Parallel Data Inputs or
3-STATE Parallel Data Outputs
RE
X
X
H
L
L
L
L
S/P
H
H
H
X
X
L
X
n
Inputs
SE
terminals are at the high impedance state; sequential operation or clearing of the register is not affected.
n
X
X
X
H
H
X
L
flip-flop prior to the last Clock LOW-to-HIGH transition.
Description
S
X
X
X
H
X
X
L
(Note 1)
OE
H
X
L
L
L
L
L
CP





X
X
2
nal on SE enables serial entry from either D
determined by the S input. A LOW signal on SE enables
shift right but Q
sign extend function required for the 74F384 Twos Com-
plement Multiplier. A HIGH signal on OE disables the 3-
STATE output buffers, regardless of the other control
inputs. In this condition the shifting and loading operations
can still be performed.
I/O
NC
D
D
O
I
L
Z
7
0
1
7
7
I/O
NC
O
O
O
I
L
Z
6
7
7
7
6
I/O
NC
O
O
O
I
L
Z
150/40 (33.3)
5
6
6
6
HIGH/LOW
7
5
3.5/1.083
reloads its contents, thus performing the
50/33.3
1.0/1.0
1.0/1.0
1.0/3.0
1.0/2.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
U.L.
I/O
NC
O
O
O
Outputs
I
L
Z
4
5
5
5
4
I/O
NC
O
O
O
I
L
Z
3
4
4
4
3
I/O
NC
O
O
O
I
L
Z
3 mA/24 mA (20 mA)
2
3
3
3
2
70 A/ 0.65 mA
Output I
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 1.8 mA
20 A/ 1.2 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
1 mA/ 20 mA
Input I
I/O
NC
O
O
O
I
L
Z
1
2
2
2
1
IH
OH
I/O
NC
O
O
O
I
L
Z
/I
0
0
0
/I
1
1
1
IL
0
) are isolated
OL
or D
NC
Q
O
O
O
I
L
L
1
0
0
1
1
1
, as