AK4104ET AKM [Asahi Kasei Microsystems], AK4104ET Datasheet
AK4104ET
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AK4104ET Summary of contents
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The AK4104 is a digital audio interface transmitter (DIT) which supports data rate up to 192kHz sample rate operation. The AK4104 encodes and transmits audio data according to the AES3, IEC60958, S/PDIF & EIAJ CP1201 interface standards. The AK4104 accepts ...
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CSN CCLK CDTI CDTO SDTI1 LRCK BICK CSN CCLK CDTI SDTI2 SDTI1 LRCK BICK MS0642-E-00 µP Prescaler Interface Audio Biphase Data Encoder Interface PDN Figure 1. AK4104 Block Diagram (Mode= “0”) µP Prescaler Interface Audio Biphase Data Encoder Interface PDN ...
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... Ordering Guide AK4104ET AKD4104 ■ Pin Layout MCLK 1 BICK 2 SDTI1 3 LRCK 4 PDN 5 CSN 6 CCLK 7 CDTI 8 MS0642-E-00 −20 ∼ +85°C 16pin TSSOP (0.65mm pitch) Evaluation Board for AK4104 AK4104 13 Top 12 View CDTO/ SDTI2 VDD VSS TEST4 TEST3 TEST2 ...
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No. Pin Name I/O 1 MCLK I 2 BICK I 3 SDTI1 I 4 LRCK I 5 PDN I 6 CSN I 7 CCLK I 8 CDTI I 9 TEST1 I 10 TEST2 O 11 TEST3 O 12 TEST4 O ...
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Note 1) Parameter Power Supply Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Temperature (Powered applied) Storage Temperature Note 1. All voltages with respect to ground. Note 2. MCLK, BICK, SDTI1, LRCK, PDN, CSN, CCLK, CDTI, SDTI2 ...
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VDD=2.7 ∼ 3.6V, C =20pF) L Parameter Master Clock Frequency Frequency Duty Cycle LRCK Frequency Frequency Duty Cycle Audio Interface Timing BICK Period BICK Pulse Width Low Pulse Width High BICK “↑” to LRCK Edge LRCK Edge to BICK ...
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Timing Diagram MCLK tCLKH LRCK BICK LRCK tBLR BICK SDTI MS0642-E-00 1/fCLK tCLKL 1/fs tBCK tBCKH tBCKL Figure 3. Clock Timing tLRB tSDS Figure 4. Serial Interface Timing - 7 - dCLK=tCLKH x fCLK, tCLKL x fCLK tSDH VIH ...
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CSN CCLK CDTI CDTO Figure 5. WRITE/READ Command Input Timing in 3-wire/4-wire serial mode CSN CCLK CDTI D3 CDTO Figure 6. WRITE Data Input Timing in 3-wire/4-wire serial mode CSN CCLK CDTI A1 CDTO Figure 7. READ Data Output Timing ...
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CSN CCLK CDTI CDTO D3 Figure 8. READ Data Output Timing 2 in 4-wire serial mode PDN MS0642-E- tPD Figure 9. Power-Down & Reset Timing - 9 - tCSW VIH VIL tCSH VIH VIL VIH VIL tCCZ Hi-Z ...
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Reset and Initialization The AK4104 should be reset once by bringing PDN = “L” upon power-up. It takes 8 bit clock cycles for the AK4104 to initialize after PDN pin goes “H”. ■ MCLK and LRCK Relationship For correct ...
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Audio Interface Format Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF1-0 bits as shown in Table 2 can select four serial data modes. In all modes the serial data is MSB-first, 2’s ...
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LRCK BICK(64fs SDTI(i) 23:MSB, 0:LSB ■ DIT input select The AK4104 can select 4-wire μP I/F mode (MODE bit = “0”) or 3-wire μP I/F mode (MODE bit = “1”). In 3-wire μP I/F mode, ...
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Data Transmission Format The Data transmitted on the TX outputs is formatted in blocks as shown in Figure 14. Each block consists of 192 frames. A frame of data contains two sub-frames. A sub-frame consists of 32 bits of ...
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Control Interface The AK4104 can select 4-wire μP I/F mode (MODE bit = “0”) or 3-wire μP I/F mode (MODE bit = “1”). 1.4-wire Serial mode (MODE bit = “0”, default) The internal registers may be either written ...
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P I/F mode (MODE bit = “1”) Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists of Chip Address (2bits, C1/0; fixed to “11”), Read/Write (1bit; fixed ...
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Register Map Addr Register Name 00H Control 1 01H Reserved 02H Control 2 03H TX 04H Channel Status Byte0 05H Channel Status Byte1 06H Channel Status Byte2 07H Channel Status Byte3 08H Channel Status Byte4 09H Channel Status Byte5 ...
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Register Name D7 02H Control 3 0 R/W Default 0 MODE: Mode Control 0: 4 wire mode 1: 3 wire mode SEL1-0: DIT input 00: SDTI1 input 01: SDTI2 input 10: SDTI2 input (DIT Bypass) 11: Reserved (NOTE) SEL1-0 bits ...
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Figure 19 and Figure 20 shows the system connection diagram. The evaluation board AKD4104 demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. Master Clock 64fs 24bit Audio Data fs Reset & Power down Micro Controller Figure ...
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TSSOP (Unit: mm) *5.0 ± 0 0.22 ± 0.1 0.13 M Seating Plane NOTE: Dimension "*" does not include mold flash. ■ Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: ...
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Date (YY/MM/DD) Revision 07/07/09 00 These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized ...