ZL30108LDE1 ZARLINK [Zarlink Semiconductor Inc], ZL30108LDE1 Datasheet
ZL30108LDE1
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ZL30108LDE1 Summary of contents
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... REF_SEL RST State Machine MODE_SEL Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved. ZL30108LDA ZL30108LDE1 Applications • Line card synchronization for SONET/SDH systems Description The ZL30108 SONET/SDH network interface digital ...
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Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Change Summary Changes from November2005 Issue to March 2006 Issue. Page, section, figure and table numbers refer to this current issue. Page Item 1 Changes from July 2005 Issue to October 2005 Issue. Page, section, figure and table numbers ...
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Physical Description 2.1 Pin Connections AGND REF_SEL REF0 REF1 OOR_SEL TIE_CLR Figure 2 - Pin Connections (32 pin QFN) ZL30108 ZL30108 ...
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Pin Description Pin # Name 1 GND Ground Positive Supply Voltage. +1.8 V CORE 3 LOCK Lock Indicator (Output). This output goes to a logic high when the PLL is frequency locked to the selected ...
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Pin # Name 21 C19o Clock 19.44 MHz (Output). This CMOS output is used in SONET/SDH applications. This clock output pad includes a Schmitt input which serves as a PLL feedback path; proper transmission-line termination should be applied to maintain ...
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Functional Description The ZL30108 is a SONET/SDH Network Interface DPLL, providing timing (clock) and synchronization (frame) signals to SONET/SDH network interface cards. Figure functional block diagram which is described in the following sections. 4.1 Reference Select ...
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Exceeding the threshold of any of the monitors forces the corresponding REF_FAIL pin to go high. The single cycle and coarse frequency failure flags force the DPLL into Holdover mode and feed a timer that disqualifies the reference input signal ...
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C20i Clock Accuracy 0 ppm +20 ppm -20 ppm -72 -75 -100 Figure 6 - Out-of-Range Thresholds for OOR_SEL=0 4.3 Time Interval Error (TIE) Corrector Circuit The TIE Corrector Circuit eliminates phase transients on the output clock that may occur ...
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TIE_CLR = 0 locked to REF0 REF0 REF1 Output Clock locked to REF1 REF0 REF1 Output Clock Figure 7 - Timing Diagram of Hitless Reference Switching ZL30108 TIE_CLR = 1 locked to REF0 REF0 REF1 Output Clock locked to REF1 ...
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Digital Phase Lock Loop (DPLL) The DPLL of the ZL30108 consists of a phase detector, an integrated on-chip loop filter, and a digitally controlled oscillator as shown in Figure 8. The data path from the phase detector to the ...
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Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of ...
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Control and Modes of Operation 5.1 Out of Range Selection The frequency out of range limits for the precise frequency monitoring in the reference monitors are selected by the OOR_SEL pin, see Table 2. 5.2 Modes of Operation The ...
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If the current reference experiences an disruption while the device is in Normal mode, the device will go automatically into Automatic Holdover mode. It will return to Normal mode as soon as the reference is valid again. If the reference ...
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Reference Selection The active reference input (REF0 or REF1) is selected by the REF_SEL pin as shown in Table 4. If the logic value of the REF_SEL pin is changed when the DPLL is in Normal mode, the ZL30108 ...
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Holdover Accuracy Holdover accuracy is defined as the absolute frequency accuracy of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the ZL30108, the storage value is ...
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Applications This section contains ZL30108 application specific details for power supply decoupling, clock and crystal operation, reset operation,and control operation. 7.1 Power Supply Decoupling Jitter levels on the ZL30108 output clocks may increase if the device is exposed to ...
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Crystal Oscillator Alternatively, a Crystal Oscillator may be used. A complete oscillator circuit made crystal, resistor and capacitors is shown in Figure 11. The accuracy of a crystal oscillator depends on the crystal tolerance as well ...
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Power Up Sequence The ZL30108 requires that the 3 not powered after the 1.8 V. This is to prevent the risk of latch-up due to the presence of parasitic diodes in the IO pads. Two options are ...
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Characteristics 8.1 AC and DC Electrical Characteristics Absolute Maximum Ratings* Parameter 1 Supply voltage 2 Core supply voltage 3 Voltage on any digital pin 4 Voltage on OSCi and OSCo pin 5 Current on any pin 6 Storage temperature ...
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DC Electrical Characteristics* Characteristics 8 High-level output voltage 9 Low-level output voltage * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated. AC Electrical Characteristics* - Timing ...
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AC Electrical Characteristics* - Input timing for REF0 and REF1 references (see Figure 14). Characteristics 1 2 kHz reference period 2 8 kHz reference period 3 1.544 MHz reference period 4 2.048 MHz reference period 5 8.192 MHz reference period ...
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REF<xx>P REF0/1 output clock with the same frequency as REF F8ko AC Electrical Characteristics* - Output Timing (see Figure 15). Characteristics 1 C19o delay 2 C19o pulse width low 3 F2ko delay 4 F2ko pulse width high 5 F8ko ...
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AC Electrical Characteristics* - OSCi 20 MHz Master Clock Input Characteristics 1 Oscillator Tolerance 2 4 Duty cycle 5 Rise time 6 Fall time * Supply voltage and operating temperature are as per Recommended Operating Conditions. 8.2 Performance Characteristics Performance ...
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Performance Characteristics*: Measured Output Jitter - Telcordia GR-253-CORE and ANSI T1.105.03 Jitter Generation Requirements Jitter Measurement Signal Filter OC-3 Interface 1 C19o 65 kHz to 1.3 MHz 2 12 kHz to1.3 MHz (Category II) 3 500 Hz to 1.3 MHz ...
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Zarlink Semiconductor 2003 All rights reserved ISSUE 3 ACN CDCA CDCA CDCA 30-01-2004 15-08-2005 DATE 22-08-2005 APPRD. Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...