ZL30120GGG ZARLINK [Zarlink Semiconductor Inc], ZL30120GGG Datasheet
ZL30120GGG
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ZL30120GGG Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved. Multi-Rate Line Card Synchronizer an email to ZL30120GGG ZL30120GGG2 100 Pin CABGA** **Pb Free Tin/Silver/Copper • Provides two DPLLs which have independent modes of operation (locked, free-run, holdover) and optional hitless reference switching. • ...
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Applications TM • AMCs for AdvancedTCA and MicroTCA Systems • Synchronous Ethernet • Multi-Service Edge Switches or Routers • DSLAM Line Cards • WAN Line Cards • RNC/Mobile Switching Center Line Cards • ADM Line Cards ZL30120 2 Zarlink Semiconductor ...
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Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - DPLL1 and DPLL2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Pin Description I/O Pin # Name Type Input Reference C1 ref0 I Input References (LVCMOS, Schmitt Trigger). These are input references d B2 ref1 available to both DPLL1 and DPLL2 for synchronizing output clocks. All eight A3 ref2 input references ...
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I/O Pin # Name Type J10 p1_clk0 O Programmable Synthesizer 1 - Output Clock 0 (LVCMOS). This output can be configured to provide any frequency with a multiple of 8 kHz up to 100 MHz in addition to 2 kHz. ...
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I/O Pin # Name Type G2 int_b O Interrupt Pin (LVCMOS). Indicates a change of device status prompting the processor to read the enabled interrupt service registers (ISR). This pin is an open drain, active low and requires an external ...
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I/O Pin # Name Type J2 IC Internal Connection. Connect to ground Internal Connection. Leave unconnected Power and Ground Positive Supply Voltage. +3. ...
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I/O Pin # Name Type Analog Ground. 0 Volts Input I - Input, Internally pulled down Input, Internally pulled up u ...
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Functional Description The ZL30120 Multi-Rate Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides ...
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DPLL Mode Control Both DPLL1 and DPLL2 independently support three modes of operation - free-run, normal and holdover. The mode of operation can be manually set or controlled by an automatic state machine as shown in Figure 2. Reset ...
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Ref and Sync Inputs There are eight reference clock inputs (ref0 to ref7) available to both DPLL1 and DPLL2. The selected reference input is used to synchronize the output clocks. Each of the DPLLs have independent reference selectors which ...
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Each of the ref inputs accept a single-ended LVCMOS clock with a frequency ranging from 2 kHz to 77.76 MHz. Built-in frequency detection circuitry automatically determines the frequency of the reference if its frequency is within the set of pre-defined ...
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Coarse Frequency Monitor (CFM) The CFM block monitors the reference frequency over a measurement period of 30 µs so that it can quickly detect large changes in frequency. A CFM failure (cfm_fail) is triggered when the frequency has changed by ...
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The output clocks and frame pulses derived from the low jitter APLL are always synchronous with DPLL1, and the clocks and frame pulses generated from the programmable synthesizers can be synchronized to either DPLL1 or DPLL2. This allows the ZL30120 ...
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Configurable Input-to-Output and Output-to-Output Delays The ZL30120 allows programmable static delay compensation for controlling input-to-output and output-to-output delays of its clocks and frame pulses. All of the output synthesizers (APLL, P0, P1, Feedback) locked to DPLL1 can be configured ...
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Software Configuration The ZL30120 is mainly controlled by accessing software registers through the serial peripheral interface (SPI). The device can be configured to operate in a highly automated manner which minimizes its interaction with the system’s processor ...
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Addr Register (Hex) Name 0F ref_mon_fail_mask_3 10 detected_ref_0 11 detected_ref_1 12 detected_ref_2 13 detected_ref_3 14 detected_sync_0 15 detected_sync_1 16 oor_ctrl_0 17 oor_ctrl_1 18 oor_ctrl_2 19 oor_ctrl_3 1A gst_mask_0 1B gst_mask_1 1C gst_qualif_time 1D dpll1_ctrl_0 1E dpll1_ctrl_1 ZL30120 Reset Value Description ...
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Addr Register (Hex) Name 1F dpll1_modesel 20 dpll1_refsel 21 dpll1_ref_fail_mask 22 dpll1_wait_to_restore 23 dpll1_ref_rev_ctrl 24 dpll1_ref_pri_ctrl_0 25 dpll1_ref_pri_ctrl_1 26 dpll1_ref_pri_ctrl_2 27 dpll1_ref_pri_ctrl_3 28 dpll1_lock_holdover_status 29 dpll1_pullinrange 2A dpll2_ctrl_0 2B dpll2_ctrl_1 2C dpll2_modesel 2D dpll2_refsel 2E dpll2_ref_fail_mask 2F dpll2_wait_to_restore ZL30120 Reset ...
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Addr Register (Hex) Name 30 dpll2_ref_rev_ctrl 31 dpll2_ref_pri_ctrl_0 32 dpll2_ref_pri_ctrl_1 33 dpll2_ref_pri_ctrl_2 34 dpll2_ref_pri_ctrl_3 35 dpll2_lock_holdover_status 36 p0_enable 37 p0_run 38 p0_freq_0 39 p0_freq_1 3A p0_clk0_offset90 3B p0_clk1_div 3C p0_clk1_offset90 3D p0_offset_fine 3E p0_fp0_freq 3F p0_fp0_type 40 p0_fp0_offset_0 41 p0_fp0_offset_1 ...
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Addr Register (Hex) Name 42 p0_fp0_offset_2 43 p0_fp1_freq 44 p0_fp1_type 45 p0_fp1_offset_0 46 p0_fp1_offset_1 47 p0_fp1_offset_2 48 p1_enable 49 p1_run 4A p1_freq_0 4B p1_freq_1 4C p1_clk0_offset90 4D p1_clk1_div 4E p1_clk1_offset90 4F p1_offset_fine 50 apll_enable 51 apll_run 52 apll_clk_div 53 apll_clk0_offset90 ...
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Addr Register (Hex) Name 54 apll_clk1_offset90 55 apll_offset_fine 56 apll_fp0_freq 57 apll_fp0_type 58 apll_fp0_offset_0 59 apll_fp0_offset_1 5A apll_fp0_offset_2 5B apll_fp1_freq 5C apll_fp1_type 5D apll_fp1_offset_0 5E apll_fp1_offset_1 5F apll_fp1_offset_2 60 reserved 61 reserved 62 fb_control 63 fb_offset_fine 64 reserved 65 ref_freq_mode_0 ...
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Addr Register (Hex) Name 67 custA_mult_0 68 custA_mult_1 69 custA_scm_low 6A custA_scm_high 6B custA_cfm_low_0 6C custA_cfm_low_1 6D custA_cfm_hi_0 6E custA_cfm_hi_1 6F custA_cfm_cycle 70 custA_div 71 custB_mult_0 72 custB_mult_1 73 custB_scm_low 74 custB_scm_high 75 custB_cfm_low_0 ZL30120 Reset Value Description (Hex) 00 ...
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Addr Register (Hex) Name 76 custB_cfm_low_1 77 custB_cfm_hi_0 78 custB_cfm_hi_1 79 custB_cfm_cycle 7A custB_div 7B - Reserved 7F 3.0 References AdvancedTCA, ATCA and the AdvancedTCA and ATCA logos are trademarks of the PCI Industrial Computer Manufacturers Group. This datasheet provides ...
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